Datasheet

© 2009 Microchip Technology Inc. DS39663F-page 207
PIC18F87J10 FAMILY
bit 1 RSEN/ADMSK1: Repeated Start Condition Enable bit
In Master mode:
(2)
1 = Initiate Repeated Start condition on SDAx and SCLx pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
In Slave mode (7-Bit Addressing mode):
1 = Address masking of ADD1 enabled
0 = Address masking of ADD1 disabled
In Slave mode (10-Bit Addressing mode):
1 = Address masking of ADD1 and ADD0 enabled
0 = Address masking of ADD1 and ADD0 disabled
bit 0 SEN: Start Condition Enable/Stretch Enable bit
(2)
In Master mode:
1 = Initiate Start condition on SDAx and SCLx pins. Automatically cleared by hardware.
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
REGISTER 19-5: SSPxCON2: MSSPx CONTROL REGISTER 2 (I
2
C™ MODE) (CONTINUED)
Note 1: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
2: For bits, ACKEN, RCEN, PEN, RSEN, SEN: If the I
2
C module is active, these bits may not be set (no
spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled).