PIC18F87J10 Family Data Sheet 64/80-Pin, High-Performance 1-Mbit Flash Microcontrollers with nanoWatt Technology © 2009 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC18F87J10 FAMILY 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology Special Microcontroller Features: Peripheral Highlights: • • • • • • High-Current Sink/Source 25 mA/25 mA (PORTB and PORTC) • Four Programmable External Interrupts • Four Input Change Interrupts • Two Capture/Compare/PWM (CCP) modules • Three Enhanced Capture/Compare/PWM (ECCP) modules: - One, two or four PWM outputs - Selectable polarity - Programmable dead time - Auto-shutdown and auto-restart • Two M
EUSART Comparators Timers 8/16-Bit External Bus PIC18F87J10 FAMILY PIC18F65J10 32K 16384 2048 50 11 2/3 2 Y Y 2 2 2/3 N PIC18F65J15 48K 24576 2048 50 11 2/3 2 Y Y 2 2 2/3 N PIC18F66J10 64K 32768 2048 50 11 2/3 2 Y Y 2 2 2/3 N PIC18F66J15 96K 49152 3936 50 11 2/3 2 Y Y 2 2 2/3 N PIC18F67J10 128K 65536 3936 50 11 2/3 2 Y Y 2 2 2/3 N PIC18F85J10 32K 16384 2048 66 15 2/3 2 Y Y 2 2 2/3 Y PIC18F85J15 48K 24576 2048 66 15
PIC18F87J10 FAMILY Pin Diagrams (Continued) Pins are up to 5.
PIC18F87J10 FAMILY Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 5 2.0 Guidelines for Getting Started with PIC18FJ Microcontrollers ................................................................................................... 27 3.0 Oscillator Configurations ....................................................................................
PIC18F87J10 FAMILY 1.0 DEVICE OVERVIEW This document contains device specific information for the following devices: • PIC18F65J10 • PIC18F85J10 • PIC18F65J15 • PIC18F85J15 • PIC18F66J10 • PIC18F86J10 • PIC18F66J15 • PIC18F86J15 • PIC18F67J10 • PIC18F87J10 This family introduces a new line of low-voltage devices with the main traditional advantage of all PIC18 microcontrollers – namely, high computational performance and a rich feature set – at an extremely competitive price point.
PIC18F87J10 FAMILY 1.1.6 EASY MIGRATION Regardless of the memory size, all devices share the same rich set of peripherals, allowing for a smooth migration path as applications grow and evolve. The consistent pinout scheme used throughout the entire family also aids in migrating to the next larger device. This is true when moving between the 64-pin members, between the 80-pin members, or even jumping from 64-pin to 80-pin devices.
PIC18F87J10 FAMILY TABLE 1-1: DEVICE FEATURES FOR THE PIC18F87J10 FAMILY (64-PIN DEVICES) Features PIC18F65J10 PIC18F65J15 PIC18F66J10 PIC18F66J15 PIC18F67J10 DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz 32K 48K 64K 96K 128K Program Memory (Instructions) 16384 24576 32768 49152 65536 Data Memory (Bytes) 2048 2048 2048 3936 3936 Operating Frequency Program Memory (Bytes) Interrupt Sources 27 I/O Ports Ports A, B, C, D, E, F, G Timers 5 Capture/Compare/PWM M
PIC18F87J10 FAMILY FIGURE 1-1: PIC18F6XJ10/6XJ15 (64-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> RA0:RA5(1) Data Memory (2.0, 3.
PIC18F87J10 FAMILY FIGURE 1-2: PIC18F8XJ10/8XJ15 (80-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> inc/dec logic 21 31 Level Stack System Bus Interface Address Latch PCU PCH PCL Program Counter Address Latch Program Memory (128 Kbytes) STKPTR RA0:RA5(1) Data Memory (2.0, 3.
PIC18F87J10 FAMILY TABLE 1-3: PIC18F6XJ10/6XJ15 PINOUT I/O DESCRIPTIONS Pin Number TQFP Pin Type Buffer Type MCLR 7 I ST OSC1/CLKI OSC1 39 Pin Name I CLKI OSC2/CLKO OSC2 I Master Clear (Reset) input. This pin is an active-low Reset to the device. Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; CMOS otherwise. CMOS External clock source input. Always associated with pin function OSC1.
PIC18F87J10 FAMILY TABLE 1-3: Pin Name PIC18F6XJ10/6XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number TQFP Pin Type Buffer Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0/FLT0 RB0 INT0 FLT0 48 RB1/INT1 RB1 INT1 47 RB2/INT2 RB2 INT2 46 RB3/INT3 RB3 INT3 45 RB4/KBI0 RB4 KBI0 44 RB5/KBI1 RB5 KBI1 43 RB6/KBI2/PGC RB6 KBI2 PGC 42 RB7/KBI3/PGD RB7 KBI3 PGD 37 I/O I I TTL ST ST Digital I/O.
PIC18F87J10 FAMILY TABLE 1-3: PIC18F6XJ10/6XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number TQFP Pin Type Buffer Type Description PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI RC0 T1OSO T13CKI 30 RC1/T1OSI/ECCP2/P2A RC1 T1OSI ECCP2(1) P2A(1) 29 RC2/ECCP1/P1A RC2 ECCP1 P1A 33 RC3/SCK1/SCL1 RC3 SCK1 SCL1 34 RC4/SDI1/SDA1 RC4 SDI1 SDA1 35 RC5/SDO1 RC5 SDO1 36 RC6/TX1/CK1 RC6 TX1 CK1 31 RC7/RX1/DT1 RC7 RX1 DT1 32 I/O O I ST — ST I/O I I/O O ST CMOS ST — Digital I/O.
PIC18F87J10 FAMILY TABLE 1-3: PIC18F6XJ10/6XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number TQFP Pin Type Buffer Type Description PORTD is a bidirectional I/O port. RD0/PSP0 RD0 PSP0 58 RD1/PSP1 RD1 PSP1 55 RD2/PSP2 RD2 PSP2 54 RD3/PSP3 RD3 PSP3 53 RD4/PSP4/SDO2 RD4 PSP4 SDO2 52 RD5/PSP5/SDI2/SDA2 RD5 PSP5 SDI2 SDA2 51 RD6/PSP6/SCK2/SCL2 RD6 PSP6 SCK2 SCL2 50 RD7/PSP7/SS2 RD7 PSP7 SS2 49 I/O I/O ST TTL Digital I/O. Parallel Slave Port data. I/O I/O ST TTL Digital I/O.
PIC18F87J10 FAMILY TABLE 1-3: Pin Name PIC18F6XJ10/6XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number TQFP Pin Type Buffer Type Description PORTE is a bidirectional I/O port. RE0/RD/P2D RE0 RD P2D 2 RE1/WR/P2C RE1 WR P2C 1 RE2/CS/P2B RE2 CS P2B 64 RE3/P3C RE3 P3C 63 RE4/P3B RE4 P3B 62 RE5/P1C RE5 P1C 61 RE6/P1B RE6 P1B 60 RE7/ECCP2/P2A RE7 ECCP2(2) P2A(2) 59 I/O I O ST TTL — Digital I/O. Read control for Parallel Slave Port. ECCP2 PWM output D. I/O I O ST TTL — Digital I/O.
PIC18F87J10 FAMILY TABLE 1-3: PIC18F6XJ10/6XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number TQFP Pin Type Buffer Type Description PORTF is a bidirectional I/O port. RF1/AN6/C2OUT RF1 AN6 C2OUT 17 RF2/AN7/C1OUT RF2 AN7 C1OUT 16 RF3/AN8 RF3 AN8 15 RF4/AN9 RF4 AN9 14 RF5/AN10/CVREF RF5 AN10 CVREF 13 RF6/AN11 RF6 AN11 12 RF7/SS1 RF7 SS1 11 I/O I O ST Analog — Digital I/O. Analog input 6. Comparator 2 output. I/O I O ST Analog — Digital I/O. Analog input 7.
PIC18F87J10 FAMILY TABLE 1-3: PIC18F6XJ10/6XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number TQFP Pin Type Buffer Type Description PORTG is a bidirectional I/O port. RG0/ECCP3/P3A RG0 ECCP3 P3A 3 RG1/TX2/CK2 RG1 TX2 CK2 4 RG2/RX2/DT2 RG2 RX2 DT2 5 RG3/CCP4/P3D RG3 CCP4 P3D 6 RG4/CCP5/P1D RG4 CCP5 P1D 8 I/O I/O O ST ST — Digital I/O. Capture 3 input/Compare 3 output/PWM 3 output. ECCP3 PWM output A. I/O O I/O ST — ST Digital I/O. EUSART2 asynchronous transmit.
PIC18F87J10 FAMILY TABLE 1-4: PIC18F8XJ10/8XJ15 PINOUT I/O DESCRIPTIONS Pin Number TQFP Pin Type Buffer Type MCLR 9 I ST OSC1/CLKI OSC1 49 I ST I CMOS O — O — Pin Name CLKI OSC2/CLKO OSC2 50 CLKO Description Master Clear (Reset) input. This pin is an active-low Reset to the device. Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; CMOS otherwise. External clock source input.
PIC18F87J10 FAMILY TABLE 1-4: PIC18F8XJ10/8XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
PIC18F87J10 FAMILY TABLE 1-4: PIC18F8XJ10/8XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTC is a bidirectional I/O port.
PIC18F87J10 FAMILY TABLE 1-4: PIC18F8XJ10/8XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTD is a bidirectional I/O port.
PIC18F87J10 FAMILY TABLE 1-4: PIC18F8XJ10/8XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTE is a bidirectional I/O port.
PIC18F87J10 FAMILY TABLE 1-4: PIC18F8XJ10/8XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTF is a bidirectional I/O port. RF1/AN6/C2OUT RF1 AN6 C2OUT 23 RF2/AN7/C1OUT RF2 AN7 C1OUT 18 RF3/AN8 RF3 AN8 17 RF4/AN9 RF4 AN9 16 RF5/AN10/CVREF RF5 AN10 CVREF 15 RF6/AN11 RF6 AN11 14 RF7/SS1 RF7 SS1 13 Legend: TTL ST I P = = = = I/O I O ST Analog — Digital I/O. Analog input 6. Comparator 2 output. I/O I O ST Analog — Digital I/O.
PIC18F87J10 FAMILY TABLE 1-4: PIC18F8XJ10/8XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTG is a bidirectional I/O port. RG0/ECCP3/P3A RG0 ECCP3 P3A 5 RG1/TX2/CK2 RG1 TX2 CK2 6 RG2/RX2/DT2 RG2 RX2 DT2 7 RG3/CCP4/P3D RG3 CCP4 P3D 8 RG4/CCP5/P1D RG4 CCP5 P1D 10 Legend: TTL ST I P = = = = I/O I/O O ST ST — Digital I/O. Capture 3 input/Compare 3 output/PWM 3 output. ECCP3 PWM output A. I/O O I/O ST — ST Digital I/O.
PIC18F87J10 FAMILY TABLE 1-4: PIC18F8XJ10/8XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTH is a bidirectional I/O port. RH0/A16 RH0 A16 79 RH1/A17 RH1 A17 80 RH2/A18 RH2 A18 1 RH3/A19 RH3 A19 2 RH4/AN12/P3C RH4 AN12 P3C(5) 22 RH5/AN13/P3B RH5 AN13 P3B(5) 21 RH6/AN14/P1C RH6 AN14 P1C(5) 20 RH7/AN15/P1B RH7 AN15 P1B(5) 19 Legend: TTL ST I P = = = = I/O I/O ST TTL Digital I/O. External memory address/data 16.
PIC18F87J10 FAMILY TABLE 1-4: PIC18F8XJ10/8XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTJ is a bidirectional I/O port. RJ0/ALE RJ0 ALE 62 RJ1/OE RJ1 OE 61 RJ2/WRL RJ2 WRL 60 RJ3/WRH RJ3 WRH 59 RJ4/BA0 RJ4 BA0 39 RJ5/CE RJ5 CE 40 RJ6/LB RJ6 LB 41 RJ7/UB RJ7 UB 42 I/O O ST — Digital I/O. External memory address latch enable. I/O O ST — Digital I/O. External memory output enable. I/O O ST — Digital I/O.
PIC18F87J10 FAMILY NOTES: DS39663F-page 26 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY • All VDD and VSS pins (see Section 2.2 “Power Supply Pins”) • All AVDD and AVSS pins, regardless of whether or not the analog device features are used (see Section 2.2 “Power Supply Pins”) • MCLR pin (see Section 2.3 “Master Clear (MCLR) Pin”) • ENVREG (if implemented) and VCAP/VDDCORE pins (see Section 2.
PIC18F87J10 FAMILY 2.2 2.2.1 Power Supply Pins DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS, is required. Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A 0.1 μF (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are recommended.
PIC18F87J10 FAMILY 2.4 Voltage Regulator Pins (ENVREG and VCAP/VDDCORE) The on-chip voltage regulator enable pin, ENVREG, must always be connected directly to either a supply voltage or to ground. Tying ENVREG to VDD enables the regulator, while tying it to ground disables the regulator. Refer to Section 24.3 “On-Chip Voltage Regulator” for details on connecting and using the on-chip regulator.
PIC18F87J10 FAMILY 2.6 External Oscillator Pins FIGURE 2-4: Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 3.0 “Oscillator Configurations” for details). Main Oscillator 13 The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0.
PIC18F87J10 FAMILY 3.0 OSCILLATOR CONFIGURATIONS 3.1 Oscillator Types The PIC18F87J10 family of devices can be operated in five different oscillator modes: 1. 2. HS High-Speed Crystal/Resonator HSPLL High-Speed Crystal/Resonator with Software PLL Control EC External Clock with FOSC/4 Output ECPLL External Clock with Software PLL Control INTRC Internal 31 kHz Oscillator 3. 4. 5.
PIC18F87J10 FAMILY TABLE 3-2: Osc Type HS CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Crystal Freq. Typical Capacitor Values Tested: C1 C2 4 MHz 27 pF 27 pF 8 MHz 22 pF 22 pF 20 MHz 15 pF 15 pF Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation. These values are not optimized. Different capacitor values may be required to produce acceptable oscillator operation.
PIC18F87J10 FAMILY 3.4 PLL Frequency Multiplier FIGURE 3-4: A Phase Locked Loop (PLL) circuit is provided as an option for users who want to use a lower frequency oscillator circuit, or to clock the device up to its highest rated frequency from a crystal oscillator. This may be useful for customers who are concerned with EMI due to high-frequency crystals, or users who require higher clock speeds from an internal oscillator. For these reasons, the HSPLL and ECPLL modes are available.
PIC18F87J10 FAMILY Internal Oscillator Block The PIC18F87J10 family of devices includes an internal oscillator source (INTRC) which provides a nominal 31 kHz output. The INTRC is enabled on device power-up and clocks the device during its configuration cycle until it enters operating mode.
PIC18F87J10 FAMILY 3.6.1 OSCILLATOR CONTROL REGISTER The OSCCON register (Register 3-2) controls several aspects of the device clock’s operation, both in full-power operation and in power-managed modes. The System Clock Select bits, SCS<1:0>, select the clock source. The available clock sources are the primary clock (defined by the FOSC<2:0> Configuration bits), the secondary clock (Timer1 oscillator) and the internal oscillator.
PIC18F87J10 FAMILY REGISTER 3-2: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0 U-0 U-0 U-0 R-q(1) U-0 R/W-0 R/W-0 IDLEN — — — OSTS — SCS1 SCS0 bit 7 bit 0 Legend: q = Value determined by configuration R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IDLEN: Idle Enable bit 1 = Device enters Idle mode on SLEEP instruction 0 = Device enters Sleep mode on SLEEP instruction bit 6-4 Uni
PIC18F87J10 FAMILY 3.7 Effects of Power-Managed Modes on the Various Clock Sources When PRI_IDLE mode is selected, the designated primary oscillator continues to run without interruption. For all other power-managed modes, the oscillator using the OSC1 pin is disabled. The OSC1 pin (and OSC2 pin if used by the oscillator) will stop oscillating. In secondary clock modes (SEC_RUN and SEC_IDLE), the Timer1 oscillator is operating and providing the device clock.
PIC18F87J10 FAMILY NOTES: DS39663F-page 38 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 4.0 POWER-MANAGED MODES 4.1.1 CLOCK SOURCES The PIC18F87J10 family devices provide the ability to manage power consumption by simply managing clocking to the CPU and the peripherals. In general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power.
PIC18F87J10 FAMILY 4.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Two bits indicate the current clock source and its status: OSTS (OSCCON<3>) and T1RUN (T1CON<6>). In general, only one of these bits will be set while in a given power-managed mode.
PIC18F87J10 FAMILY Note: On transitions from SEC_RUN mode to PRI_RUN, the peripherals and CPU continue to be clocked from the Timer1 oscillator while the primary clock is started. When the primary clock becomes ready, a clock switch back to the primary clock occurs (see Figure 4-2). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run.
PIC18F87J10 FAMILY 4.2.3 RC_RUN MODE On transitions from RC_RUN mode to PRI_RUN mode, the device continues to be clocked from the INTRC while the primary clock is started. When the primary clock becomes ready, a clock switch to the primary clock occurs (see Figure 4-4). When the clock switch is complete, the OSTS bit is set and the primary clock is providing the device clock. The IDLEN and SCS bits are not affected by the switch.
PIC18F87J10 FAMILY 4.3 Sleep Mode 4.4 The power-managed Sleep mode is identical to the legacy Sleep mode offered in all other PIC devices. It is entered by clearing the IDLEN bit (the default state on device Reset) and executing the SLEEP instruction. This shuts down the selected oscillator (Figure 4-5). All clock source status bits are cleared. Idle Modes The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to operate.
PIC18F87J10 FAMILY 4.4.1 PRI_IDLE MODE 4.4.2 This mode is unique among the three low-power Idle modes, in that it does not disable the primary device clock. For timing-sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to “warm up” or transition from another oscillator. PRI_IDLE mode is entered from PRI_RUN mode by setting the IDLEN bit and executing a SLEEP instruction.
PIC18F87J10 FAMILY 4.4.3 RC_IDLE MODE In RC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the internal oscillator. This mode allows for controllable power conservation during Idle periods. From RC_RUN, this mode is entered by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, first set IDLEN, then clear the SCS bits and execute SLEEP.
PIC18F87J10 FAMILY NOTES: DS39663F-page 46 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 5.0 RESET 5.1 The PIC18F87J10 family of devices differentiate between various kinds of Reset: a) b) c) d) e) f) g) h) Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during power-managed modes Watchdog Timer (WDT) Reset (during execution) Brown-out Reset (BOR) RESET Instruction Stack Full Reset Stack Underflow Reset RCON Register Device Reset events are tracked through the RCON register (Register ).
PIC18F87J10 FAMILY REGISTER 5-1: RCON: RESET CONTROL REGISTER R/W-0 U-0 U-0 R/W-1 R-1 R-1 R/W-0 R/W-0 IPEN — — RI TO PD POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6-5 Unimplemented: Read as ‘0’
PIC18F87J10 FAMILY 5.2 Master Clear (MCLR) FIGURE 5-2: The MCLR pin provides a method for triggering a hard external Reset of the device. A Reset is generated by holding the pin low. PIC18 extended microcontroller devices have a noise filter in the MCLR Reset path which detects and ignores small pulses. 5.3 D C POR events are captured by the POR bit (RCON<1>). The state of the bit is set to ‘0’ whenever a POR occurs; it does not change for any other Reset event.
PIC18F87J10 FAMILY 5.5 Power-up Timer (PWRT) 5.5.1 PIC18F87J10 family devices incorporate an on-chip Power-up Timer (PWRT) to help regulate the Power-on Reset process. The PWRT is always enabled. The main function is to ensure that the device voltage is stable before code is executed. The Power-up Timer (PWRT) of the PIC18F87J10 family devices is an 11-bit counter which uses the INTRC source as the clock input. This yields an approximate time interval of 2048 x 32 μs = 65.6 ms.
PIC18F87J10 FAMILY FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET FIGURE 5-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) 3.3V VDD 0V 1V MCLR INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 5.6 Reset State of Registers Table 5-2 describes the Reset states for all of the Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups. Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred.
PIC18F87J10 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt TOSU PIC18F6XJ1X PIC18F8XJ1X ---0 0000 ---0 0000 ---0 uuuu(1) TOSH PIC18F6XJ1X PIC18F8XJ1X 0000 0000 0000 0000 uuuu uuuu(1) TOSL PIC18F6XJ1X PIC18F8XJ1X 0000 0000 0000 0000 uuuu uuuu(1) STKPTR PIC18F6XJ1X PIC18F8XJ1X 00-0 0000 uu-0 0000 uu-u uuuu(1) PCLATU PIC18F6XJ1X PIC18F8XJ1
PIC18F87J10 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt INDF2 PIC18F6XJ1X PIC18F8XJ1X N/A N/A N/A POSTINC2 PIC18F6XJ1X PIC18F8XJ1X N/A N/A N/A POSTDEC2 PIC18F6XJ1X PIC18F8XJ1X N/A N/A N/A PREINC2 PIC18F6XJ1X PIC18F8XJ1X N/A N/A N/A PLUSW2 PIC18F6XJ1X PIC18F8XJ1X N/A N/A N/A FSR2H PIC18F6XJ1X PIC18F8XJ1X -
PIC18F87J10 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt CCPR1H PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx uuuu uuuu uuuu uuuu CCPR1L PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON PIC18F6XJ1X PIC18F8XJ1X 0000 0000 0000 0000 uuuu uuuu CCPR2H PIC18F6XJ1X PIC18F8XJ1X xxxx xxxx uuuu uuuu uuuu uuuu CCPR2L PIC18F6XJ1X PIC
PIC18F87J10 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt TRISJ PIC18F6XJ1X PIC18F8XJ1X 1111 1111 1111 1111 uuuu uuuu TRISH PIC18F6XJ1X PIC18F8XJ1X 1111 1111 1111 1111 uuuu uuuu TRISG PIC18F6XJ1X PIC18F8XJ1X ---1 1111 ---1 1111 ---u uuuu TRISF PIC18F6XJ1X PIC18F8XJ1X 1111 111- 1111 111- uuuu uuu- TRISE PIC18F6XJ1X PIC18F8XJ
PIC18F87J10 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt ECCP1DEL PIC18F6XJ1X PIC18F8XJ1X 0000 0000 0000 0000 uuuu uuuu TMR4 PIC18F6XJ1X PIC18F8XJ1X 0000 0000 0000 0000 uuuu uuuu PR4 PIC18F6XJ1X PIC18F8XJ1X 1111 1111 1111 1111 1111 1111 T4CON PIC18F6XJ1X PIC18F8XJ1X -000 0000 -000 0000 -uuu uuuu CCPR4H PIC18F6XJ1X PIC18F8X
PIC18F87J10 FAMILY NOTES: DS39663F-page 58 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 6.0 MEMORY ORGANIZATION 6.1 There are two types of memory in PIC18 Flash microcontroller devices: • Program Memory • Data RAM As Harvard architecture devices, the data and program memories use separate busses; this allows for concurrent access of the two memory spaces. Additional detailed information on the operation of the Flash program memory is provided in Section 7.0 “Flash Program Memory”.
PIC18F87J10 FAMILY 6.1.1 HARD MEMORY VECTORS 6.1.2 FLASH CONFIGURATION WORDS All PIC18 devices have a total of three hard-coded return vectors in their program memory space. The Reset vector address is the default value to which the program counter returns on all device Resets; it is located at 0000h. Because PIC18F87J10 family devices do not have persistent configuration memory, the top four words of on-chip program memory are reserved for configuration information.
PIC18F87J10 FAMILY 6.1.3 PIC18F8XJ10/8XJ15 PROGRAM MEMORY MODES The 80-pin devices in this family can address up to a total of 2 Mbytes of program memory. This is achieved through the external memory bus. There are two distinct operating modes available to the controllers: • Microcontroller (MC) • Extended Microcontroller (EMC) The program memory mode is determined by setting the EMB Configuration bits (CONFIG3L<5:4>), as shown in Register 6-1. (See also Section 24.
PIC18F87J10 FAMILY 6.1.4 EXTENDED MICROCONTROLLER MODE AND ADDRESS SHIFTING To avoid this, the Extended Microcontroller mode implements an address shifting option to enable automatic address translation. In this mode, addresses presented on the external bus are shifted down by the size of the on-chip program memory and are remapped to start at 0000h. This allows the complete use of the external memory device’s memory space.
PIC18F87J10 FAMILY 6.1.5 PROGRAM COUNTER The Program Counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21 bits wide and is contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC<15:8> bits; it is not directly readable or writable. Updates to the PCH register are performed through the PCLATH register. The upper byte is called PCU.
PIC18F87J10 FAMILY 6.1.6.2 Return Stack Pointer (STKPTR) When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and set the STKUNF bit, while the Stack Pointer remains at zero. The STKUNF bit will remain set until cleared by software or until a POR occurs. The STKPTR register (Register 6-2) contains the Stack Pointer value, the STKFUL (Stack Full) status bit and the STKUNF (Stack Underflow) status bit.
PIC18F87J10 FAMILY 6.1.6.4 Stack Full and Underflow Resets Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in Configuration Register 1L. When STVREN is set, a full or underflow condition will set the appropriate STKFUL or STKUNF bit and then cause a device Reset. When STVREN is cleared, a full or underflow condition will set the appropriate STKFUL or STKUNF bit, but not cause a device Reset.
PIC18F87J10 FAMILY 6.2 PIC18 Instruction Cycle 6.2.1 6.2.2 An “Instruction Cycle” consists of four Q cycles, Q1 through Q4. The instruction fetch and execute are pipelined in such a manner that a fetch takes one instruction cycle, while the decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g.
PIC18F87J10 FAMILY 6.2.3 INSTRUCTIONS IN PROGRAM MEMORY The program memory is addressed in bytes. Instructions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSB = 0). To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSB will always read ‘0’ (see Section 6.1.5 “Program Counter”).
PIC18F87J10 FAMILY 6.3 Note: Data Memory Organization The operation of some aspects of data memory are changed when the PIC18 extended instruction set is enabled. See Section 6.6 “Data Memory and the Extended Instruction Set” for more information. The data memory in PIC18 devices is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. The memory space is divided into as many as 16 banks that contain 256 bytes each.
PIC18F87J10 FAMILY FIGURE 6-7: DATA MEMORY MAP FOR PIC18FX5J10/X5J15/X6J10 DEVICES When a = 0: BSR<3:0> Data Memory Map 00h = 0000 = 0001 = 0010 = 0011 = 0100 = 0101 = 0110 = 0111 Bank 0 FFh 00h Bank 1 Access RAM GPR GPR 1FFh 200h FFh 00h Bank 2 GPR FFh 00h Bank 3 2FFh 300h Bank 4 = 1111 The second 160 bytes are Special Function Registers (from Bank 15). When a = 1: The BSR specifies the bank used by the instruction.
PIC18F87J10 FAMILY FIGURE 6-8: DATA MEMORY MAP FOR PIC18FX6J15/X7J10 DEVICES When a = 0: BSR<3:0> Data Memory Map 00h = 0000 = 0001 = 0010 = 0011 = 0100 = 0101 = 0110 = 0111 = 1000 = 1001 = 1010 = 1011 = 1100 = 1101 = 1110 = 1111 DS39663F-page 70 Bank 0 FFh 00h Bank 1 Access RAM GPR GPR 1FFh 200h FFh 00h Bank 2 GPR FFh 00h Bank 3 2FFh 300h The first 96 bytes are general purpose RAM (from Bank 0). The remaining 160 bytes are Special Function Registers (from Bank 15).
PIC18F87J10 FAMILY FIGURE 6-9: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) BSR(1) 7 0 0 0 0 0 0 0 Bank Select(2) 1 0 000h Data Memory Bank 0 100h Bank 1 200h 300h Bank 2 00h 7 FFh 00h 11 From Opcode(2) 11 11 11 11 1 0 1 1 FFh 00h FFh 00h Bank 3 through Bank 13 E00h Bank 14 F00h FFFh Note 1: 2: 6.3.2 Bank 15 FFh 00h FFh 00h FFh The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank.
PIC18F87J10 FAMILY 6.3.4 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFRs) are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. SFRs start at the top of data memory (FFFh) and extend downward to occupy more than the top half of Bank 15 (F60h to FFFh). A list of these registers is given in Table 6-3 and Table 6-4.
PIC18F87J10 FAMILY TABLE 6-4: File Name REGISTER FILE SUMMARY (PIC18F87J10 FAMILY) Bit 7 Bit 6 Bit 5 — — — Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Details on page: ---0 0000 53, 63 TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 53, 63 TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 53, 63 00-0 0000 53, 64 ---0 0000 53, 63 53, 63 TOSU STKPTR STKFUL STKUNF — PCLATU — — bit 21(1) Top-of-Stack Upper Byte (TOS<20:16>) Value on POR, BOR SP4 SP3 SP2 SP1 SP0 Holding Register for
PIC18F87J10 FAMILY TABLE 6-4: File Name REGISTER FILE SUMMARY (PIC18F87J10 FAMILY) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page: TMR0H Timer0 Register High Byte 0000 0000 54, 153 TMR0L Timer0 Register Low Byte xxxx xxxx 54, 153 54, 151 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 OSCCON IDLEN — — — OSTS(5) — SCS1 SCS0 0--- q-00 36, 54 WDTCON — — — — — — — SWDTEN --- ---0 54, 287 IPEN — — R
PIC18F87J10 FAMILY TABLE 6-4: File Name TXREG1 REGISTER FILE SUMMARY (PIC18F87J10 FAMILY) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EUSART1 Transmit Register Value on POR, BOR Details on page: xxxx xxxx 55, 249, 250 TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 55, 240 RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 55, 241 ---- ---- 55 EECON2 EECON1 IPR3 Program Memory Control Register 2 (not a physical register) — — — FREE WR
PIC18F87J10 FAMILY TABLE 6-4: File Name SPBRGH1 BAUDCON1 SPBRGH2 REGISTER FILE SUMMARY (PIC18F87J10 FAMILY) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BRG16 — WUE ABDEN EUSART1 Baud Rate Generator Register High Byte ABDOVF RCIDL — SCKP EUSART2 Baud Rate Generator Register High Byte Value on POR, BOR Details on page: 0000 0000 56, 243 01-0 0-00 56, 242 0000 0000 56, 243 BAUDCON2 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 56, 242 ECCP1DEL P1RSEN P1D
PIC18F87J10 FAMILY 6.3.5 STATUS REGISTER The STATUS register, shown in Register 6.4, contains the arithmetic status of the ALU. The STATUS register can be the operand for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, then the write to these five bits is disabled. These bits are set or cleared according to the device logic.
PIC18F87J10 FAMILY 6.4 Data Addressing Modes Note: The execution of some instructions in the core PIC18 instruction set are changed when the PIC18 extended instruction set is enabled. See Section 6.6 “Data Memory and the Extended Instruction Set” for more information. While the program memory can be addressed in only one way – through the program counter – information in the data memory space can be addressed in several ways. For most instructions, the addressing mode is fixed.
PIC18F87J10 FAMILY 6.4.3.1 FSR Registers and the INDF Operand the SFR space but are not physically implemented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read from INDF1, for example, reads the data at the address indicated by FSR1H:FSR1L. Instructions that use the INDF registers as operands actually use the contents of their corresponding FSR as a pointer to the instruction’s target.
PIC18F87J10 FAMILY 6.4.3.2 FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW In addition to the INDF operand, each FSR register pair also has four additional indirect operands. Like INDF, these are “virtual” registers that cannot be indirectly read or written to. Accessing these registers actually accesses the associated FSR register pair, but also performs a specific action on its stored value.
PIC18F87J10 FAMILY 6.5 Program Memory and the Extended Instruction Set The operation of program memory is unaffected by the use of the extended instruction set. Enabling the extended instruction set adds five additional two-word commands to the existing PIC18 instruction set: ADDFSR, CALLW, MOVSF, MOVSS and SUBFSR. These instructions are executed as described in Section 6.2.4 “Two-Word Instructions”. 6.
PIC18F87J10 FAMILY FIGURE 6-11: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff) When a = 0 and f ≥ 60h: The instruction executes in Direct Forced mode. ‘f’ is interpreted as a location in the Access RAM between 060h and FFFh. This is the same as locations F60h to FFFh (Bank 15) of data memory. Locations below 060h are not available in this addressing mode.
PIC18F87J10 FAMILY 6.6.3 MAPPING THE ACCESS BANK IN INDEXED LITERAL OFFSET MODE The use of Indexed Literal Offset Addressing mode effectively changes how the lower part of Access RAM (00h to 5Fh) is mapped. Rather than containing just the contents of the bottom part of Bank 0, this mode maps the contents from Bank 0 and a user-defined “window” that can be located anywhere in the data memory space.
PIC18F87J10 FAMILY NOTES: DS39663F-page 84 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 7.0 FLASH PROGRAM MEMORY 7.1 Table Reads and Table Writes The Flash program memory is readable, writable and erasable during normal operation over the entire VDD range. In order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data RAM: A read from program memory is executed on one byte at a time. A write to program memory is executed on blocks of 64 bytes at a time.
PIC18F87J10 FAMILY FIGURE 7-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) TBLPTRU TBLPTRH Table Latch (8-bit) TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: The Table Pointer actually points to one of 64 holding registers, the address of which is determined by TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in Section 7.5 “Writing to Flash Program Memory”. 7.
PIC18F87J10 FAMILY REGISTER 7-1: EECON1: EEPROM CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0 R/W-x R/W-0 R/S-0 U-0 — — — FREE WRERR WREN WR — bit 7 bit 0 Legend: S = Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 FREE: Flash Erase Enable bit 1 = Erase the program memory block addressed by TBLPTR on the next WR command (cleared by compl
PIC18F87J10 FAMILY 7.2.2 TABLE LATCH REGISTER (TABLAT) 7.2.4 The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 7.2.3 TBLPTR is used in reads, writes and erases of the Flash program memory. When a TBLRD is executed, all 22 bits of the TBLPTR determine which byte is read from program memory into TABLAT.
PIC18F87J10 FAMILY 7.3 Reading the Flash Program Memory TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The TBLRD instruction is used to retrieve data from program memory and places it into data RAM. Table reads from program memory are performed one byte at a time. FIGURE 7-4: The internal program memory is typically organized by words.
PIC18F87J10 FAMILY 7.4 Erasing Flash Program Memory The minimum erase block is 512 words or 1024 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be bulk erased. Word erase in the Flash array is not supported. When initiating an erase sequence from the microcontroller itself, a block of 1024 bytes of program memory is erased. The Most Significant 12 bits of the TBLPTR<21:10> point to the block being erased. TBLPTR<9:0> are ignored.
PIC18F87J10 FAMILY 7.5 Writing to Flash Program Memory The on-chip timer controls the write time. The write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device. The minimum programming block is 32 words or 64 bytes. Word or byte programming is not supported. Table writes are used internally to load the holding registers needed to program the Flash memory. There are 64 holding registers used by the table writes for programming.
PIC18F87J10 FAMILY EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; Load TBLPTR with the base address ; of the memory block, minus 1 BSF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF MOVLW MOVWF EECON1, WREN EECON1, FREE INTCON, GIE 55h EECON2 0AAh EECON2 EECON1, WR INTCON, GIE D'16' WRITE_COUNTER ; enable write to memory ; enable Erase operation ; disable interrupts MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF D
PIC18F87J10 FAMILY 7.5.2 7.6 WRITE VERIFY Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. 7.5.3 Flash Program Operation During Code Protection See Section 24.6 “Program Verification and Code Protection” for details on code protection of Flash program memory.
PIC18F87J10 FAMILY NOTES: DS39663F-page 94 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 8.0 EXTERNAL MEMORY BUS Note: The external memory bus implemented on 64-pin devices. is not The external memory bus allows the device to access external memory devices (such as Flash, EPROM, SRAM, etc.) as program or data memory. It supports both 8 and 16-Bit Data Width modes and three address widths of up to 20 bits. TABLE 8-1: The bus is implemented with 28 pins, multiplexed across four I/O ports.
PIC18F87J10 FAMILY 8.1 External Memory Bus Control The operation of the interface is controlled by the MEMCON register (Register 8-1). This register is available in all program memory operating modes except Microcontroller mode. In this mode, the register is disabled and cannot be written to. The EBDIS bit (MEMCON<7>) controls the operation of the bus and related port functions.
PIC18F87J10 FAMILY 8.2 Address and Data Width 8.2.1 The PIC18F87J10 family of devices can be independently configured for different address and data widths on the same memory bus. Both address and data width are set by Configuration bits in the CONFIG3L register. As Configuration bits, this means that these options can only be configured by programming the device and are not controllable in software. The BW bit selects an 8-bit or 16-bit data bus width.
PIC18F87J10 FAMILY 8.3 Wait States While it may be assumed that external memory devices will operate at the microcontroller clock rate, this is often not the case. In fact, many devices require longer times to write or retrieve data than the time allowed by the execution of table read or table write operations. To compensate for this, the external memory bus can be configured to add a fixed delay to each table operation using the bus. Wait states are enabled by setting the WAIT Configuration bit.
PIC18F87J10 FAMILY 8.6.1 16-BIT BYTE WRITE MODE During a TBLWT instruction cycle, the TABLAT data is presented on the upper and lower bytes of the AD<15:0> bus. The appropriate WRH or WRL control line is strobed on the LSb of the TBLPTR. Figure 8-1 shows an example of 16-Bit Byte Write mode for PIC18F87J10 family devices. This mode is used for two separate 8-bit memories connected for 16-bit operation. This generally includes basic EPROM and Flash devices.
PIC18F87J10 FAMILY 8.6.2 16-BIT WORD WRITE MODE Figure 8-2 shows an example of 16-Bit Word Write mode for PIC18F65J10 devices. This mode is used for word-wide memories which include some of the EPROM and Flash type memories. This mode allows opcode fetches and table reads from all forms of 16-bit memory and table writes to any type of word-wide external memories. This method makes a distinction between TBLWT cycles to even or odd addresses.
PIC18F87J10 FAMILY 8.6.3 16-BIT BYTE SELECT MODE Figure 8-3 shows an example of 16-Bit Byte Select mode. This mode allows table write operations to word-wide external memories with byte selection capability. This generally includes both word-wide Flash and SRAM devices. During a TBLWT cycle, the TABLAT data is presented on the upper and lower byte of the AD<15:0> bus. The WRH signal is strobed for each write cycle; the WRL pin is not used.
PIC18F87J10 FAMILY 8.6.4 16-BIT MODE TIMING The presentation of control signals on the external memory bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure 8-4 and Figure 8-5.
PIC18F87J10 FAMILY 8.7 8-Bit Mode will enable one byte of program memory for a portion of the instruction cycle, then BA0 will change and the second byte will be enabled to form the 16-bit instruction word. The Least Significant bit of the address, BA0, must be connected to the memory devices in this mode. The Chip Enable signal (CE) is active at any time that the microcontroller accesses external memory, whether reading or writing. It is inactive (asserted high) whenever the device is in Sleep mode.
PIC18F87J10 FAMILY 8.7.1 8-BIT MODE TIMING The presentation of control signals on the external memory bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure 8-7 and Figure 8-8.
PIC18F87J10 FAMILY 8.8 Operation in Power-Managed Modes In alternate power-managed Run modes, the external bus continues to operate normally. If a clock source with a lower speed is selected, bus operations will run at that speed. In these cases, excessive access times for the external memory may result if wait states have been enabled and added to external memory operations.
PIC18F87J10 FAMILY NOTES: DS39663F-page 106 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 9.0 8 x 8 HARDWARE MULTIPLIER 9.1 Introduction EXAMPLE 9-1: MOVF MULWF All PIC18 devices include an 8 x 8 hardware multiplier as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, PRODH:PRODL. The multiplier’s operation does not affect any flags in the STATUS register. ARG1, W ARG2 EXAMPLE 9-2: Making multiplication a hardware operation allows it to be completed in a single instruction cycle.
PIC18F87J10 FAMILY Example 9-3 shows the sequence to do a 16 x 16 unsigned multiplication. Equation 9-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0).
PIC18F87J10 FAMILY 10.0 INTERRUPTS Members of the PIC18F87J10 family of devices have multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high-priority level or a low-priority level. The high-priority interrupt vector is at 0008h and the low-priority interrupt vector is at 0018h. High-priority interrupt events will interrupt any low-priority interrupts that may be in progress.
PIC18F87J10 FAMILY FIGURE 10-1: PIC18F87J10 FAMILY INTERRUPT LOGIC Wake-up if in Idle or Sleep modes TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:6, 3:0> PIE2<7:6, 3:0> IPR2<7:6, 3:0> Interrupt to CPU Vector to Location 0008h GIE/GIEH IPEN PIR3<7, 0> PIE3<7, 0> IPR3<7, 0> IPEN PEIE/GIEL IPEN High-Priority Interrupt Generation Low-Priority Interrupt Generation PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<
PIC18F87J10 FAMILY 10.1 INTCON Registers Note: The INTCON registers are readable and writable registers which contain various enable, priority and flag bits. REGISTER 10-1: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.
PIC18F87J10 FAMILY REGISTER 10-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External In
PIC18F87J10 FAMILY REGISTER 10-3: INTCON3: INTERRUPT CONTROL REGISTER 3 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low
PIC18F87J10 FAMILY 10.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Request (Flag) registers (PIR1, PIR2, PIR3). REGISTER 10-4: Note 1: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE (INTCON<7>).
PIC18F87J10 FAMILY REGISTER 10-5: R/W-0 OSCFIF PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 R/W-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 CMIF — — BCL1IF — TMR3IF CCP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = Device oscillator failed, clock input has changed to INTRC (must be cleared in software) 0 = Device cl
PIC18F87J10 FAMILY REGISTER 10-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SSP2IF: Master Synchronous Serial Port 2 Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in softwa
PIC18F87J10 FAMILY 10.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Enable registers (PIE1, PIE2, PIE3). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts.
PIC18F87J10 FAMILY REGISTER 10-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 OSCFIE CMIE — — BCL1IE — TMR3IE CCP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 CMIE: Comparator Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5-4 Unimplemented: Read as
PIC18F87J10 FAMILY REGISTER 10-9: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SSP2IE: Master Synchronous Serial Port 2 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 BCL2IE: Bus Collision Interrupt Enable bit (MSSP2 module) 1 =
PIC18F87J10 FAMILY 10.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority registers (IPR1, IPR2, IPR3). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set.
PIC18F87J10 FAMILY REGISTER 10-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 R/W-1 U-0 U-0 R/W-1 U-0 R/W-1 R/W-1 OSCFIP CMIP — — BCL1IP — TMR3IP CCP2IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 CMIP: Comparator Interrupt Priority bit 1 = High priority 0 = Low priority bit 5-4
PIC18F87J10 FAMILY REGISTER 10-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SSP2IP: Master Synchronous Serial Port 2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 BCL2IP: Bus Collision Interrupt Priority bit
PIC18F87J10 FAMILY 10.5 RCON Register The RCON register contains bits used to determine the cause of the last Reset or wake-up from Idle or Sleep modes. RCON also contains the bit that enables interrupt priorities (IPEN).
PIC18F87J10 FAMILY 10.6 INTx Pin Interrupts 10.7 TMR0 Interrupt External interrupts on the RB0/INT0, RB1/INT1, RB2/INT2 and RB3/INT3 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit, INTxIF, is set. This interrupt can be disabled by clearing the corresponding enable bit, INTxIE.
PIC18F87J10 FAMILY 11.0 I/O PORTS 11.1 I/O Port Pin Capabilities Depending on the device selected and features enabled, there are up to nine ports available. Some pins of the I/O ports are multiplexed with an alternate function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. When developing an application, the capabilities of the port pins must be considered.
PIC18F87J10 FAMILY 11.1.2 INPUT PINS AND VOLTAGE CONSIDERATIONS The voltage tolerance of pins used as device inputs is dependent on the pin’s input function. Pins that are used as digital only inputs are able to handle DC voltages up to 5.5V, a level typical for digital logic circuits. In contrast, pins that also have analog input functions of any kind can only tolerate voltages up to VDD. Voltage excursions beyond VDD on these pins should be avoided. Table 11-2 summarizes the input capabilities.
PIC18F87J10 FAMILY TABLE 11-3: Pin Name RA0/AN0 PORTA FUNCTIONS Function TRIS Setting I/O RA0 RA1/AN1 RA2/AN2/VREF- RA3/AN3/VREF+ RA4/T0CKI RA5/AN4 Description 0 O DIG LATA<0> data output; not affected by analog input. 1 I TTL PORTA<0> data input; disabled when analog input enabled. AN0 1 I ANA A/D Input Channel 0. Default input configuration on POR; does not affect digital output. RA1 0 O DIG LATA<1> data output; not affected by analog input.
PIC18F87J10 FAMILY 11.3 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). All pins on PORTB are digital only and tolerate voltages up to 5.5V.
PIC18F87J10 FAMILY TABLE 11-5: PORTB FUNCTIONS Pin Name Function TRIS Setting I/O I/O Type RB0/INT0/FLT0 RB0 0 O DIG LATB<0> data output. 1 I TTL PORTB<0> data input; weak pull-up when RBPU bit is cleared. 1 I ST External Interrupt 0 input. INT0 RB1/INT1 RB2/INT2 RB3/INT3/ ECCP2/P2A RB4/KBI0 FLT0 1 I ST Enhanced PWM Fault input (ECCP1 module); enabled in software. RB1 0 O DIG LATB<1> data output. 1 I TTL PORTB<1> data input; weak pull-up when RBPU bit is cleared.
PIC18F87J10 FAMILY TABLE 11-6: Name PORTB SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 56 LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 56 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 56 TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53 INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 53 INT2IF INT1IF 53 INTCON GIE/GIEH PEIE/GIEL INTCON2
PIC18F87J10 FAMILY 11.4 PORTC, TRISC and LATC Registers PORTC is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin).
PIC18F87J10 FAMILY TABLE 11-7: PORTC FUNCTIONS Pin Name Function TRIS Setting I/O I/O Type RC0/T1OSO/ T13CKI RC0 0 O DIG RC1/T1OSI/ ECCP2/P2A 1 I ST x O ANA T13CKI 1 I ST Timer1/Timer3 counter input. RC1 0 O DIG LATC<1> data output. 1 I ST x I ANA Timer1 oscillator input; enabled when Timer1 oscillator enabled. Disables digital I/O. ECCP2(1) 0 O DIG CCP2 compare output and CCP2 PWM output; takes priority over port data. 1 I ST CCP2 capture input.
PIC18F87J10 FAMILY TABLE 11-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 56 LATC LATC7 LATBC6 LATC5 LATCB4 LATC3 LATC2 LATC1 LATC0 56 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 56 Name PORTC © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 11.5 PORTD, TRISD and LATD Registers PORTD is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i.e., put the contents of the output latch on the selected pin). All pins on PORTD are digital only and tolerate voltages up to 5.5V.
PIC18F87J10 FAMILY TABLE 11-9: PORTD FUNCTIONS Pin Name Function TRIS Setting I/O I/O Type RD0/AD0/PSP0 RD0 0 O DIG LATD<0> data output. 1 I ST PORTD<0> data input. x O DIG External memory interface, address/data bit 0 output.(1) x I TTL External memory interface, data bit 0 input.(1) (2) AD0 PSP0 RD1/AD1/PSP1 O DIG PSP read output data (LATD<0>); takes priority over port data. I TTL PSP write data input. 0 O DIG LATD<1> data output. 1 I ST PORTD<1> data input.
PIC18F87J10 FAMILY TABLE 11-9: Pin Name RD6/AD6/ PSP6/SCK2/ SCL2 PORTD FUNCTIONS (CONTINUED) Function TRIS Setting I/O I/O Type RD6 0 O DIG LATD<6> data output. PORTD<6> data input. AD6(2) PSP6 SCK2 SCL2 RD7 RD7/AD7/ PSP7/SS2 Note 1: 2: 1 I ST x O DIG-3 x I TTL External memory interface, data bit 6 input.(1) x O DIG PSP read output data (LATD<6>); takes priority over port data. x I TTL PSP write data input.
PIC18F87J10 FAMILY 11.6 PORTE, TRISE and LATE Registers PORTE is a 7-bit wide, bidirectional port. The corresponding Data Direction register is TRISE. Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output (i.e., put the contents of the output latch on the selected pin). All pins on PORTE are digital only and tolerate voltages up to 5.5V.
PIC18F87J10 FAMILY TABLE 11-11: Pin Name PORTE FUNCTIONS Function TRIS Setting I/O I/O Type RE0 0 O DIG LATE<0> data output. 1 I ST PORTE<0> data input. x O DIG External memory interface, address/data bit 8 output.(2) x I TTL External memory interface, data bit 8 input.(2) RE0/AD8/RD/ P2D AD8(3) RE1/AD9/WR/ P2C RD 1 I TTL Parallel Slave Port read enable control input. P2D 0 O DIG ECCP2 Enhanced PWM output, Channel D; takes priority over port and PSP data.
PIC18F87J10 FAMILY TABLE 11-11: Pin Name RE6/AD14/ P1B PORTE FUNCTIONS (CONTINUED) Function TRIS Setting I/O I/O Type RE6 0 O DIG LATE<6> data output. 1 I ST PORTE<6> data input. x O DIG External memory interface, address/data bit 14 output.(2) x I TTL External memory interface, data bit 14 input.(2) P1B(1) 0 O DIG ECCP1 Enhanced PWM output, Channel B; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events.
PIC18F87J10 FAMILY 11.7 PORTF, LATF and TRISF Registers PORTF is a 7-bit wide, bidirectional port. The corresponding Data Direction register is TRISF. Setting a TRISF bit (= 1) will make the corresponding PORTF pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISF bit (= 0) will make the corresponding PORTF pin an output (i.e., put the contents of the output latch on the selected pin).
PIC18F87J10 FAMILY TABLE 11-13: PORTF FUNCTIONS Pin Name RF1/AN6/ C2OUT RF2/AN7/ C1OUT RF3/AN8 RF4/AN9 RF5/AN10/ CVREF RF6/AN11 RF7/SS1 Function TRIS Setting I/O I/O Type RF1 0 O DIG LATF<1> data output; not affected by analog input. 1 I ST PORTF<1> data input; disabled when analog input enabled. AN6 1 I ANA A/D Input Channel 6. Default configuration on POR. C2OUT 0 O DIG Comparator 2 output; takes priority over port data.
PIC18F87J10 FAMILY 11.8 PORTG, TRISG and LATG Registers PORTG is a 5-bit wide, bidirectional port. The corresponding Data Direction register is TRISG. Setting a TRISG bit (= 1) will make the corresponding PORTG pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISG bit (= 0) will make the corresponding PORTG pin an output (i.e., put the contents of the output latch on the selected pin). All pins on PORTG are digital only and tolerate voltages up to 5.5V.
PIC18F87J10 FAMILY TABLE 11-15: PORTG FUNCTIONS Pin Name RG0/ECCP3/ P3A Function TRIS Setting I/O I/O Type RG0 0 O DIG 1 I ST PORTG<0> data input. O DIG CCP3 compare and PWM output; takes priority over port data. I ST CCP3 capture input. ECCP3 RG1/TX2/CK2 RG2/RX2/DT2 RG3/CCP4/ P3D RG4/CCP5/ P1D LATG<0> data output. P3A 0 O DIG ECCP3 Enhanced PWM output, Channel A; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events.
PIC18F87J10 FAMILY 11.9 Note: PORTH, LATH and TRISH Registers PORTH is available only on 80-pin devices. When the external memory interface is enabled, four of the PORTH pins function as the high-order address lines for the interface. The address output from the interface takes priority over other digital I/O. The corresponding TRISH bits are also overridden. PORTH is an 8-bit wide, bidirectional I/O port. The corresponding Data Direction register is TRISH.
PIC18F87J10 FAMILY TABLE 11-17: PORTH FUNCTIONS Pin Name RH0/A16 RH1/A17 RH2/A18 RH3/A19 RH4/AN12/P3C Function TRIS Setting I/O I/O Type RH0 0 O DIG 1 I ST PORTH<0> data input. A16 x O DIG External memory interface, address line 16. Takes priority over port data. RH1 0 O DIG LATH<1> data output. 1 I ST PORTH<1> data input. A17 x O DIG External memory interface, address line 17. Takes priority over port data. RH2 0 O DIG LATH<2> data output.
PIC18F87J10 FAMILY 11.10 PORTJ, TRISJ and LATJ Registers Note: PORTJ is available only on 80-pin devices. PORTJ is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISJ. Setting a TRISJ bit (= 1) will make the corresponding PORTJ pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISJ bit (= 0) will make the corresponding PORTJ pin an output (i.e., put the contents of the output latch on the selected pin).
PIC18F87J10 FAMILY TABLE 11-19: PORTJ FUNCTIONS Pin Name RJ0/ALE RJ1/OE RJ2/WRL RJ3/WRH RJ4/BA0 RJ5/CE RJ6/LB RJ7/UB Function TRIS Setting I/O I/O Type RJ0 0 O DIG LATJ<0> data output. 1 I ST PORTJ<0> data input. ALE x O DIG External memory interface address latch enable control output; takes priority over digital I/O. RJ1 0 O DIG LATJ<1> data output. 1 I ST PORTJ<1> data input.
PIC18F87J10 FAMILY 11.11 Parallel Slave Port PORTD can also function as an 8-bit wide Parallel Slave Port, or microprocessor port, when control bit, PSPMODE (PSPCON<4>), is set. It is asynchronously readable and writable by the external world through RD control input pin (RE0/RD) and WR control input pin (RE1/WR). Note: For 80-pin devices, the Parallel Slave Port is available only in Microcontroller mode. The PSP can directly interface to an 8-bit microprocessor data bus.
PIC18F87J10 FAMILY REGISTER 11-1: PSPCON: PARALLEL SLAVE PORT CONTROL REGISTER R-0 R-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 IBF OBF IBOV PSPMODE — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IBF: Input Buffer Full Status bit 1 = A word has been received and is waiting to be read by the CPU 0 = No word has been received bit 6 OBF: Output Buffer Full Status b
PIC18F87J10 FAMILY FIGURE 11-4: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 11-21: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Name PORTD Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 56 LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 56 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 56 PORTE RE7 RE6 RE5 RE4
PIC18F87J10 FAMILY 12.0 TIMER0 MODULE The Timer0 module incorporates the following features: • Software-selectable operation as a timer or counter in both 8-bit or 16-bit modes • Readable and writable registers • Dedicated 8-bit, software programmable prescaler • Selectable clock source (internal or external) • Edge select for external clock • Interrupt-on-overflow REGISTER 12-1: The T0CON register (Register 12-1) controls all aspects of the module’s operation, including the prescale selection.
PIC18F87J10 FAMILY 12.1 Timer0 Operation Timer0 can operate as either a timer or a counter. The mode is selected with the T0CS bit (T0CON<5>). In Timer mode (T0CS = 0), the module increments on every clock by default unless a different prescaler value is selected (see Section 12.3 “Prescaler”). If the TMR0 register is written to, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register.
PIC18F87J10 FAMILY 12.3 Prescaler 12.3.1 An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not directly readable or writable. Its value is set by the PSA and T0PS<2:0> bits (T0CON<3:0>) which determine the prescaler assignment and prescale ratio. Clearing the PSA bit assigns the prescaler to the Timer0 module. When it is assigned, prescale values from 1:2 through 1:256 in power-of-2 increments are selectable.
PIC18F87J10 FAMILY NOTES: DS39663F-page 154 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 13.
PIC18F87J10 FAMILY 13.1 Timer1 Operation cycle (FOSC/4). When the bit is set, Timer1 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator, if enabled. Timer1 can operate in one of these modes: • Timer • Synchronous Counter • Asynchronous Counter When Timer1 is enabled, the RC1/T1OSI and RC0/T1OSO/T13CKI pins become inputs. This means the values of TRISC<1:0> are ignored and the pins are read as ‘0’.
PIC18F87J10 FAMILY 13.2 Timer1 16-Bit Read/Write Mode Timer1 can be configured for 16-bit reads and writes (see Figure 13-2). When the RD16 control bit (T1CON<7>) is set, the address for TMR1H is mapped to a buffer register for the high byte of Timer1. A read from TMR1L will load the contents of the high byte of Timer1 into the Timer1 High Byte Buffer register.
PIC18F87J10 FAMILY 13.3.3 TIMER1 OSCILLATOR LAYOUT CONSIDERATIONS The Timer1 oscillator circuit draws very little power during operation. Due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. The oscillator circuit, shown in Figure 13-3, should be located as close as possible to the microcontroller. There should be no circuits passing within the oscillator circuit boundaries other than VSS or VDD.
PIC18F87J10 FAMILY EXAMPLE 13-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE RTCinit MOVLW MOVWF CLRF MOVLW MOVWF CLRF CLRF MOVLW MOVWF BSF RETURN 80h TMR1H TMR1L b’00001111’ T1CON secs mins .12 hours PIE1, TMR1IE BSF BCF INCF MOVLW CPFSGT RETURN CLRF INCF MOVLW CPFSGT RETURN CLRF INCF MOVLW CPFSGT RETURN CLRF RETURN TMR1H, 7 PIR1, TMR1IF secs, F .
PIC18F87J10 FAMILY NOTES: DS39663F-page 160 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 14.0 TIMER2 MODULE 14.1 Timer2 Operation • 8-Bit Timer and Period registers (TMR2 and PR2, respectively) • Readable and writable (both registers) • Software programmable prescaler (1:1, 1:4 and 1:16) • Software programmable postscaler (1:1 through 1:16) • Interrupt on TMR2 to PR2 match • Optional use as the shift clock for the MSSP module In normal operation, TMR2 is incremented from 00h on each clock (FOSC/4).
PIC18F87J10 FAMILY 14.2 Timer2 Interrupt 14.3 Timer2 can also generate an optional device interrupt. The Timer2 output signal (TMR2 to PR2 match) provides the input for the 4-bit output counter/postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF (PIR1<1>). The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE (PIE1<1>).
PIC18F87J10 FAMILY 15.0 TIMER3 MODULE The Timer3 timer/counter module incorporates these features: • Software selectable operation as a 16-bit timer or counter • Readable and writable 8-bit registers (TMR3H and TMR3L) • Selectable clock source (internal or external) with device clock or Timer1 oscillator internal options • Interrupt-on-overflow • Module Reset on CCP Special Event Trigger REGISTER 15-1: A simplified block diagram of the Timer3 module is shown in Figure 15-1.
PIC18F87J10 FAMILY 15.1 Timer3 Operation The operating mode is determined by the clock select bit, TMR3CS (T3CON<1>). When TMR3CS is cleared (= 0), Timer3 increments on every internal instruction cycle (FOSC/4). When the bit is set, Timer3 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator, if enabled.
PIC18F87J10 FAMILY 15.2 Timer3 16-Bit Read/Write Mode 15.4 Timer3 Interrupt Timer3 can be configured for 16-bit reads and writes (see Figure 15-2). When the RD16 control bit (T3CON<7>) is set, the address for TMR3H is mapped to a buffer register for the high byte of Timer3. A read from TMR3L will load the contents of the high byte of Timer3 into the Timer3 High Byte Buffer register.
PIC18F87J10 FAMILY NOTES: DS39663F-page 166 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 16.0 TIMER4 MODULE 16.1 The Timer4 timer module has the following features: • • • • • • 8-Bit Timer register (TMR4) 8-Bit Period register (PR4) Readable and writable (both registers) Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) Interrupt on TMR4 match of PR4 Timer4 has a control register shown in Register 16-1. Timer4 can be shut off by clearing control bit, TMR4ON (T4CON<2>), to minimize power consumption.
PIC18F87J10 FAMILY 16.2 Timer4 Interrupt 16.3 The Timer4 module has an 8-Bit Period register, PR4, which is both readable and writable. Timer4 increments from 00h until it matches PR4 and then resets to 00h on the next increment cycle. The PR4 register is initialized to FFh upon Reset. FIGURE 16-1: Output of TMR4 The output of TMR4 (before the postscaler) is used only as a PWM time base for the CCP modules. It is not used as a baud rate clock for the MSSP as is the Timer2 output.
PIC18F87J10 FAMILY 17.0 CAPTURE/COMPARE/PWM (CCP) MODULES register. For the sake of clarity, all CCP module operation in the following sections is described with respect to CCP4, but is equally applicable to CCP5. Members of the PIC18F87J10 family of devices all have a total of five CCP (Capture/Compare/PWM) modules. Two of these (CCP4 and CCP5) implement standard Capture, Compare and Pulse-Width Modulation (PWM) modes and are discussed in this section.
PIC18F87J10 FAMILY 17.1 CCP Module Configuration Each Capture/Compare/PWM module is associated with a control register (generically, CCPxCON) and a data register (CCPRx). The data register, in turn, is comprised of two 8-bit registers: CCPRxL (low byte) and CCPRxH (high byte). All registers are both readable and writable. 17.1.1 17.1.2 CCP MODULES AND TIMER RESOURCES The CCP/ECCP modules utilize Timers 1, 2, 3 or 4, depending on the mode selected.
PIC18F87J10 FAMILY 17.2 Capture Mode 17.2.3 When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit clear to avoid false interrupts. The interrupt flag bit, CCPxIF, should also be cleared following any such change in operating mode. In Capture mode, the CCPRxH:CCPRxL register pair captures the 16-bit value of the TMR1 or TMR3 registers when an event occurs on the corresponding CCPx pin.
PIC18F87J10 FAMILY 17.3 Compare Mode Note: In Compare mode, the 16-Bit CCPRx register value is constantly compared against either the TMR1 or TMR3 register pair value. When a match occurs, the CCPx pin can be: • • • • driven high driven low toggled (high-to-low or low-to-high) remains unchanged (that is, reflects the state of the I/O latch) 17.3.2 17.3.3 SOFTWARE INTERRUPT MODE When the Generate Software Interrupt mode is chosen (CCPxM<3:0> = 1010), the corresponding CCPx pin is not affected.
PIC18F87J10 FAMILY TABLE 17-2: Name INTCON REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Bit 7 Bit 6 Bit 5 GIE/GIEH PEIE/GIEL TMR0IE Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INT0IE RBIE TMR0IF INT0IF RBIF 53 RCON IPEN — — RI TO PD POR BOR 54 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 55 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 55 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 55 PIR2 OSCF
PIC18F87J10 FAMILY 17.4 PWM Mode 17.4.1 In Pulse-Width Modulation (PWM) mode, the CCPx pin produces up to a 10-bit resolution PWM output. Since the CCP4 and CCP5 pins are multiplexed with a PORTG data latch, the appropriate TRISG bit must be cleared to make the CCP4 or CCP5 pin an output. Note: Clearing the CCP4CON or CCP5CON register will force the RG3 or RG4 output latch (depending on device configuration) to the default low level. This is not the PORTG I/O data latch.
PIC18F87J10 FAMILY The CCPRxH register and a 2-bit internal latch are used to double-buffer the PWM duty cycle. This double-buffering is essential for glitchless PWM operation. When the CCPRxH and 2-bit latch match TMR2 (TMR4), concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 (TMR4) prescaler, the CCPx pin is cleared. The maximum PWM resolution (bits) for a given PWM frequency is given by Equation 17-3: 17.4.
PIC18F87J10 FAMILY TABLE 17-4: Name INTCON REGISTERS ASSOCIATED WITH PWM, TIMER2 AND TIMER4 Bit 7 Bit 6 GIE/GIEH PEIE/GIEL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53 IPEN — — RI TO PD POR BOR 54 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 55 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 55 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 55 RCON PIR3 SSP2IF BCL2IF
PIC18F87J10 FAMILY 18.0 ENHANCED CAPTURE/ COMPARE/PWM (ECCP) MODULE The control register for the Enhanced CCP module is shown in Register 18-1. It differs from the CCP4CON/ CCP5CON registers in that the two Most Significant bits are implemented to control PWM functionality. In the PIC18F87J10 family of devices, three of the CCP modules are implemented as standard CCP modules with Enhanced PWM capabilities.
PIC18F87J10 FAMILY 18.1 ECCP Outputs and Configuration Each of the Enhanced CCP modules may have up to four PWM outputs, depending on the selected operating mode. These outputs, designated PxA through PxD, are multiplexed with various I/O pins. Some ECCP pin assignments are constant, while others change based on device configuration.
PIC18F87J10 FAMILY TABLE 18-1: PIN CONFIGURATIONS FOR ECCP1 CCP1CON Configuration ECCP Mode RC2 RE6 RE5 RG4 RH7 RH6 All PIC18F6XJ10/6XJ15 Devices: Compatible CCP 00xx 11xx ECCP1 RE6 RE5 RG4/CCP5 N/A N/A Dual PWM 10xx 11xx P1A P1B RE5 RG4/CCP5 N/A N/A Quad PWM x1xx 11xx P1A P1B P1C P1D N/A N/A PIC18F8XJ10/8XJ15 Devices, ECCPMX = 0, Microcontroller mode: Compatible CCP 00xx 11xx ECCP1 RE6/AD14 RE5/AD13 RG4/CCP5 RH7/AN15 RH6/AN14 Dual PWM 10xx 11xx P1A RE6/AD14 RE5/
PIC18F87J10 FAMILY TABLE 18-3: PIN CONFIGURATIONS FOR ECCP3 CCP3CON Configuration ECCP Mode RG0 RE4 RE3 RG3 RH5 RH4 All PIC18F6XJ10/6XJ15 Devices: Compatible CCP 00xx 11xx ECCP3 RE4 RE3 RG3/CCP4 N/A N/A Dual PWM 10xx 11xx P3A P3B RE3 RG3/CCP4 N/A N/A Quad PWM x1xx 11xx P3A P3B P3C P3D N/A N/A PIC18F8XJ10/8XJ15 Devices, ECCPMX = 0, Microcontroller mode: Compatible CCP 00xx 11xx ECCP3 RE6/AD14 RE5/AD13 RG3/CCP4 RH7/AN15 RH6/AN14 Dual PWM 10xx 11xx P3A RE6/AD14 RE5/
PIC18F87J10 FAMILY 18.4 Enhanced PWM Mode The Enhanced PWM mode provides additional PWM output options for a broader range of control applications. The module is a backward compatible version of the standard CCP module and offers up to four outputs, designated PxA through PxD. Users are also able to select the polarity of the signal (either active-high or active-low).
PIC18F87J10 FAMILY 18.4.2 PWM DUTY CYCLE Note: The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The PWM duty cycle is calculated by the equation: 18.4.
PIC18F87J10 FAMILY FIGURE 18-2: PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) CCP1CON<7:6> SIGNAL 0 PR2 + 1 Duty Cycle Period 00 (Single Output) P1A Modulated Delay(1) Delay(1) P1A Modulated (Half-Bridge) 10 P1B Modulated P1A Active (Full-Bridge, Forward) 01 P1B Inactive P1C Inactive P1D Modulated P1A Inactive (Full-Bridge, Reverse) 11 P1B Modulated P1C Active P1D Inactive FIGURE 18-3: PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) CCP1CON<7:6> SIGNAL 0 Duty Cycle PR2 + 1 Period 00 (
PIC18F87J10 FAMILY 18.4.4 HALF-BRIDGE MODE FIGURE 18-4: In the Half-Bridge Output mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the P1A pin, while the complementary PWM output signal is output on the P1B pin (Figure 18-4). This mode can be used for half-bridge applications, as shown in Figure 18-5, or for full-bridge applications, where four power switches are being modulated with two PWM signals.
PIC18F87J10 FAMILY 18.4.5 FULL-BRIDGE MODE In Full-Bridge Output mode, four pins are used as outputs; however, only two outputs are active at a time. In the Forward mode, pin P1A is continuously active and pin P1D is modulated. In the Reverse mode, pin P1C is continuously active and pin P1B is modulated. These are illustrated in Figure 18-6. FIGURE 18-6: P1A, P1B, P1C and P1D outputs are multiplexed with the port pins as described in Table 18-1, Table 18-2 and Table 18-3.
PIC18F87J10 FAMILY FIGURE 18-7: EXAMPLE OF FULL-BRIDGE APPLICATION V+ PIC18F87J10 FET Driver QC QA FET Driver P1A Load P1B FET Driver P1C FET Driver QD QB VP1D 18.4.5.1 Direction Change in Full-Bridge Mode In the Full-Bridge Output mode, the P1M1 bit in the CCP1CON register allows users to control the forward/ reverse direction. When the application firmware changes this direction control bit, the module will assume the new direction on the next PWM cycle.
PIC18F87J10 FAMILY FIGURE 18-8: PWM DIRECTION CHANGE Period(1) SIGNAL Period P1A (Active-High) P1B (Active-High) DC P1C (Active-High) (Note 2) P1D (Active-High) DC Note 1: The direction bit in the ECCP1 Control register (CCP1CON<7>) is written at any time during the PWM cycle. 2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at intervals of 4 TOSC, 16 TOSC or 64 TOSC, depending on the Timer2 prescaler value.
PIC18F87J10 FAMILY 18.4.6 PROGRAMMABLE DEAD-BAND DELAY In half-bridge applications, where all power switches are modulated at the PWM frequency at all times, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on and the other turned off), both switches may be on for a short period of time until one switch completely turns off.
PIC18F87J10 FAMILY REGISTER 18-3: ECCPxAS: ENHANCED CCPx AUTO-SHUTDOWN CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ECCPxASE ECCPxAS2 ECCPxAS1 ECCPxAS0 PSSxAC1 PSSxAC0 PSSxBD1 PSSxBD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ECCPxASE: ECCPx Auto-Shutdown Event Status bit 1 = A shutdown event has occurred; ECCPx outputs are in a shutd
PIC18F87J10 FAMILY The P1A, P1B, P1C and P1D output latches may not be in the proper states when the PWM module is initialized. Enabling the PWM pins for output at the same time as the ECCP1 module may cause damage to the application circuit. The ECCP1 module must be enabled in the FIGURE 18-10: proper output mode and complete a full PWM cycle before configuring the PWM pins as outputs. The completion of a full PWM cycle is indicated by the TMR2IF bit being set as the second PWM period begins.
PIC18F87J10 FAMILY 18.4.9 SETUP FOR PWM OPERATION The following steps should be taken when configuring the ECCPx module for PWM operation: 1. 2. 3. 4. 5. 6. 7. Configure the PWM pins, PxA and PxB (and PxC and PxD, if used), as inputs by setting the corresponding TRIS bits. Set the PWM period by loading the PR2 (PR4) register.
PIC18F87J10 FAMILY TABLE 18-5: Name INTCON RCON REGISTERS ASSOCIATED WITH ECCP MODULES AND TIMER1 TO TIMER4 Reset Values on page Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53 IPEN — — RI TO PD POR BOR 54 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 55 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 55 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 55 PIR2 OSCFI
PIC18F87J10 FAMILY 19.0 19.1 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE Master SSP (MSSP) Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D Converters, etc.
PIC18F87J10 FAMILY 19.3.1 REGISTERS SSPxSR is the shift register used for shifting data in or out. SSPxBUF is the buffer register to which data bytes are written to or read from. Each MSSP module has four registers for SPI mode operation. These are: In receive operations, SSPxSR and SSPxBUF together create a double-buffered receiver. When SSPxSR receives a complete byte, it is transferred to SSPxBUF and the SSPxIF interrupt is set.
PIC18F87J10 FAMILY REGISTER 19-2: R/W-0 SSPxCON1: MSSPx CONTROL REGISTER 1 (SPI MODE) R/W-0 WCOL SSPOV (1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit 1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in
PIC18F87J10 FAMILY 19.3.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>).
PIC18F87J10 FAMILY 19.3.3 ENABLING SPI I/O To enable the serial port, MSSP Enable bit, SSPEN (SSPxCON1<5>), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, reinitialize the SSPxCON registers and then set the SSPEN bit. This configures the SDIx, SDOx, SCKx and SSx pins as serial port pins.
PIC18F87J10 FAMILY 19.3.5 MASTER MODE The master can initiate the data transfer at any time because it controls the SCKx. The master determines when the slave (Processor 1, Figure 19-2) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPxBUF register is written to. If the SPI is only going to receive, the SDOx output could be disabled (programmed as an input).
PIC18F87J10 FAMILY 19.3.6 SLAVE MODE In Slave mode, the data is transmitted and received as the external clock pulses appear on SCKx. When the last bit is latched, the SSPxIF interrupt flag bit is set. While in Slave mode, the external clock is supplied by the external clock source on the SCKx pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. While in Sleep mode, the slave can transmit/receive data.
PIC18F87J10 FAMILY FIGURE 19-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SSx Optional SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF SDOx SDIx (SMP = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 bit 7 Input Sample (SMP = 0) SSPxIF Interrupt Flag Next Q4 Cycle after Q2↓ SSPxSR to SSPxBUF FIGURE 19-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SSx Not Optional SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 1) Write to SSPxBUF SDOx bit 7 SDIx (SMP = 0) bit 7 bi
PIC18F87J10 FAMILY 19.3.8 OPERATION IN POWER-MANAGED MODES In SPI Master mode, module clocks may be operating at a different speed than when in Full-Power mode; in the case of the Sleep mode, all clocks are halted. In Idle modes, a clock is provided to the peripherals. That clock can be from the primary clock source, the secondary clock (Timer1 oscillator) or the INTOSC source. See Section 3.6 “Clock Sources and Oscillator Switching” for additional information. 19.3.
PIC18F87J10 FAMILY TABLE 19-2: Name INTCON REGISTERS ASSOCIATED WITH SPI OPERATION Bit 7 Bit 6 Bit 5 GIE/GIEH PEIE/GIEL TMR0IE Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INT0IE RBIE TMR0IF INT0IF RBIF 53 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 55 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 55 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 55 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 55 PIE3
PIC18F87J10 FAMILY 19.4 I2C Mode 19.4.1 The MSSP module in I 2C mode fully implements all master and slave functions (including general call support) and provides interrupts on Start and Stop bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing.
PIC18F87J10 FAMILY REGISTER 19-3: R/W-0 SSPxSTAT: MSSPx STATUS REGISTER (I2C™ MODE) R/W-0 SMP CKE R-0 R-0 R-0 R-0 R-0 R-0 D/A P(1) S(1) R/W(2,3) UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for High
PIC18F87J10 FAMILY REGISTER 19-4: SSPxCON1: MSSPx CONTROL REGISTER 1 (I2C™ MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPxBUF register was attempted while the I2C conditions were no
PIC18F87J10 FAMILY REGISTER 19-5: SSPxCON2: MSSPx CONTROL REGISTER 2 (I2C™ MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT/ ADMSK5(1) ACKEN/ ADMSK4 RCEN/ ADMSK3 PEN/ ADMSK2 RSEN/ ADMSK1 SEN(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GCEN: General Call Enable bit (Slave mode only) 1 = Enable interrupt when a general call address
PIC18F87J10 FAMILY REGISTER 19-5: SSPxCON2: MSSPx CONTROL REGISTER 2 (I2C™ MODE) (CONTINUED) bit 1 RSEN/ADMSK1: Repeated Start Condition Enable bit In Master mode:(2) 1 = Initiate Repeated Start condition on SDAx and SCLx pins. Automatically cleared by hardware.
PIC18F87J10 FAMILY REGISTER 19-6: SSPxADD: MSSP1 and MSSP2 ADDRESS REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: x = Bit is unknown ADD<7:0>: MSSP Address bits MSSP1 and MSSP2 Address register in I2C Slave mode.
PIC18F87J10 FAMILY 19.4.2 OPERATION The MSSP module functions are enabled by setting MSSP Enable bit, SSPEN (SSPxCON1<5>). The SSPxCON1 register allows control of the I2C operation.
PIC18F87J10 FAMILY 19.4.3.2 Address Masking Masking an address bit causes that bit to become a “don’t care”. When one address bit is masked, two addresses will be Acknowledged and cause an interrupt. It is possible to mask more than one address bit at a time, which makes it possible to Acknowledge up to 31 addresses in 7-bit mode and up to 63 addresses in 10-bit mode (see Example 19-2). The I2C slave behaves the same way whether address masking is used or not.
PIC18F87J10 FAMILY 19.4.3.3 Reception When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPxSTAT register is cleared. The received address is loaded into the SSPxBUF register and the SDAx line is held low (ACK). When the address byte overflow condition exists, then the no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit, BF (SSPxSTAT<0>), is set, or bit, SSPOV (SSPxCON1<6>), is set.
DS39663F-page 212 2 A6 CKP 3 4 A4 5 A3 Receiving Address A5 6 A2 (CKP does not reset to ‘0’ when SEN = 0) SSPOV (SSPxCON1<6>) BF (SSPxSTAT<0>) SSPxIF (PIR1<3> or PIR3<7>) 1 SCLx S A7 7 A1 8 9 ACK R/W = 0 1 D7 3 4 D4 5 D3 Receiving Data D5 Cleared in software SSPxBUF is read 2 D6 6 D2 7 D1 8 D0 9 ACK 1 D7 2 D6 3 4 D4 5 D3 Receiving Data D5 6 D2 7 D1 8 D0 Bus master terminates transfer P SSPOV is set because SSPxBUF is still full. ACK is not sent.
© 2009 Microchip Technology Inc. 2 A6 Note CKP 3 A5 4 X 5 A3 6 X 1 3 4 D4 Cleared in software SSPxBUF is read 2 D5 5 D3 6 D2 7 D1 8 D0 In this example, an address equal to A7.A6.A5.X.A3.X.X will be Acknowledged and cause an interrupt. 9 D6 x = Don’t care (i.e., address bit can be either a ‘1’ or a ‘0’).
DS39663F-page 214 2 Data in sampled 1 A6 CKP (SSPxCON<4>) BF (SSPxSTAT<0>) SSPxIF (PIR1<3> or PIR3<7>) S A7 3 4 A4 5 A3 6 A2 Receiving Address A5 7 A1 8 R/W = 0 9 ACK 3 D5 4 5 D3 SSPxBUF is written in software 6 D2 Transmitting Data D4 Cleared in software 2 D6 CKP is set in software Clear by reading SCLx held low while CPU responds to SSPxIF 1 D7 7 8 D0 9 From SSPxIF ISR D1 ACK 1 D7 4 D4 5 D3 Cleared in software 3 D5 6 D2 CKP is set in software SS
© 2009 Microchip Technology Inc. 2 1 3 1 Note 5 0 7 A8 8 UA is set indicating that the SSPxADD needs to be updated SSPxBUF is written with contents of SSPxSR 6 A9 9 2 X 4 5 A3 6 A2 4 5 6 Cleared in software 3 7 8 9 1 2 4 5 6 Cleared in software 3 D3 D2 Receive Data Byte D1 D0 ACK D7 D6 D5 D4 Cleared by hardware when SSPxADD is updated with high byte of address 2 D3 D2 Note that the Most Significant bits of the address are not affected by the bit masking.
DS39663F-page 216 2 1 3 1 5 0 7 A8 8 UA is set indicating that the SSPxADD needs to be updated SSPxBUF is written with contents of SSPxSR 6 A9 9 (CKP does not reset to ‘0’ when SEN = 0) UA (SSPxSTAT<1>) SSPOV (SSPxCON1<6>) BF (SSPxSTAT<0>) CKP 4 1 Cleared in software SSPxIF (PIR1<3> or PIR3<7>) 1 SCLx S 1 ACK R/W = 0 A7 2 4 A4 5 A3 6 A2 8 9 A0 ACK UA is set indicating that SSPxADD needs to be updated Cleared by hardware when SSPxADD is updated with low byte of addres
© 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 19.4.4 CLOCK STRETCHING Both 7-Bit and 10-Bit Slave modes implement automatic clock stretching during a transmit sequence. The SEN bit (SSPxCON2<0>) allows clock stretching to be enabled during receives. Setting SEN will cause the SCLx pin to be held low at the end of each data receive sequence. 19.4.4.
PIC18F87J10 FAMILY 19.4.4.5 Clock Synchronization and the CKP Bit When the CKP bit is cleared, the SCLx output is forced to ‘0’. However, clearing the CKP bit will not assert the SCLx output low until the SCLx output is already sampled low. Therefore, the CKP bit will not assert the SCLx line until an external I2C master device has FIGURE 19-14: already asserted the SCLx line. The SCLx output will remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCLx.
DS39663F-page 220 2 A6 CKP SSPOV (SSPxCON1<6>) BF (SSPxSTAT<0>) SSPxIF (PIR1<3> or PIR3<7>) 1 SCLx S A7 3 4 A4 5 A3 6 A2 Receiving Address A5 7 A1 8 9 ACK R/W = 0 3 4 D4 5 D3 Receiving Data D5 Cleared in software 2 D6 If BF is cleared prior to the falling edge of the 9th clock, CKP will not be reset to ‘0’ and no clock stretching will occur SSPxBUF is read 1 D7 6 D2 7 D1 9 ACK 1 D7 BF is set after falling edge of the 9th clock, CKP is reset to ‘0’ and clock stre
© 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 19.4.5 GENERAL CALL ADDRESS SUPPORT If the general call address matches, the SSPxSR is transferred to the SSPxBUF, the BF flag bit is set (eighth bit) and on the falling edge of the ninth bit (ACK bit), the SSPxIF interrupt flag bit is set. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master. The exception is the general call address which can address all devices.
PIC18F87J10 FAMILY MASTER MODE Note: Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPxCON1 and by setting the SSPEN bit. In Master mode, the SCLx and SDAx lines are manipulated by the MSSP hardware if the TRIS bits are set. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled.
PIC18F87J10 FAMILY 19.4.6.1 I2C Master Mode Operation The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDAx, while SCLx outputs the serial clock.
PIC18F87J10 FAMILY 19.4.7 BAUD RATE 19.4.7.1 2 In I C Master mode, the Baud Rate Generator (BRG) reload value is placed in the lower 7 bits of the SSPxADD register (Figure 19-19). When a write occurs to SSPxBUF, the Baud Rate Generator will automatically begin counting. The BRG counts down to 0 and stops until another reload has taken place. The BRG count is decremented twice per instruction cycle (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the BRG is reloaded automatically.
PIC18F87J10 FAMILY 19.4.7.2 Clock Arbitration Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, deasserts the SCLx pin (SCLx allowed to float high). When the SCLx pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCLx pin is actually sampled high. When the FIGURE 19-20: SCLx pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<6:0> and begins counting.
PIC18F87J10 FAMILY 19.4.8 I2C MASTER MODE START CONDITION TIMING Note: To initiate a Start condition, the user sets the Start Enable bit, SEN (SSPxCON2<0>). If the SDAx and SCLx pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<6:0> and starts its count. If SCLx and SDAx are both sampled high when the Baud Rate Generator times out (TBRG), the SDAx pin is driven low.
PIC18F87J10 FAMILY 19.4.9 I2C MASTER MODE REPEATED START CONDITION TIMING Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. A Repeated Start condition occurs when the RSEN bit (SSPxCON2<1>) is programmed high and the I2C logic module is in the Idle state. When the RSEN bit is set, the SCLx pin is asserted low. When the SCLx pin is sampled low, the Baud Rate Generator is loaded with the contents of SSPxADD<5:0> and begins counting.
PIC18F87J10 FAMILY 19.4.10 I2C MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address, or the other half of a 10-bit address, is accomplished by simply writing a value to the SSPxBUF register. This action will set the Buffer Full flag bit, BF, and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDAx pin after the falling edge of SCLx is asserted (see data hold time specification parameter 106).
DS39663F-page 230 S R/W PEN SEN BF (SSPxSTAT<0>) SSPxIF SCLx SDAx A6 A5 A4 A3 A2 A1 3 4 5 Cleared in software 2 6 7 8 After Start condition, SEN cleared by hardware SSPxBUF written 1 9 D7 1 SCLx held low while CPU responds to SSPxIF ACK = 0 R/W = 0 SSPxBUF written with 7-bit address and R/W, start transmit A7 Transmit Address to Slave 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 SSPxBUF is written in software Cleared in software service routine from MSSP interrupt 2 D6 Trans
© 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 19.4.12 ACKNOWLEDGE SEQUENCE TIMING 19.4.13 A Stop bit is asserted on the SDAx pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN (SSPxCON2<2>). At the end of a receive/transmit, the SCLx line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDAx line low. When the SDAx line is sampled low, the Baud Rate Generator is reloaded and counts down to ‘0’.
PIC18F87J10 FAMILY 19.4.14 SLEEP OPERATION 19.4.17 2 While in Sleep mode, the I C module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled). 19.4.15 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. 19.4.
PIC18F87J10 FAMILY 19.4.17.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDAx or SCLx are sampled low at the beginning of the Start condition (Figure 19-28). SCLx is sampled low before SDAx is asserted low (Figure 19-29). During a Start condition, both the SDAx and the SCLx pins are monitored. If the SDAx pin is sampled low during this count, the BRG is reset and the SDAx line is asserted early (Figure 19-30).
PIC18F87J10 FAMILY FIGURE 19-29: BUS COLLISION DURING START CONDITION (SCLx = 0) SDAx = 0, SCLx = 1 TBRG TBRG SDAx Set SEN, enable Start sequence if SDAx = 1, SCLx = 1 SCLx SCLx = 0 before SDAx = 0, bus collision occurs. Set BCLxIF. SEN SCLx = 0 before BRG time-out, bus collision occurs. Set BCLxIF.
PIC18F87J10 FAMILY 19.4.17.2 Bus Collision During a Repeated Start Condition If SDAx is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ‘0’, Figure 19-31). If SDAx is sampled high, the BRG is reloaded and begins counting. If SDAx goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDAx at exactly the same time.
PIC18F87J10 FAMILY 19.4.17.3 Bus Collision During a Stop Condition The Stop condition begins with SDAx asserted low. When SDAx is sampled low, the SCLx pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPxADD<6:0> and counts down to 0. After the BRG times out, SDAx is sampled. If SDAx is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ‘0’ (Figure 19-33).
PIC18F87J10 FAMILY TABLE 19-4: Name INTCON REGISTERS ASSOCIATED WITH I2C™ OPERATION Bit 7 Bit 6 Bit 5 GIE/GIEH PEIE/GIEL TMR0IE Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page INT0IE RBIE TMR0IF INT0IF RBIF 53 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 55 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 55 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 55 PIR2 OSCFIF CMIF — — BCL1IF — TMR3IF CCP2IF 55 PIE2 OSCFIE CMIE
PIC18F87J10 FAMILY 20.0 ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART) The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is one of two serial I/O modules. (Generically, the EUSART is also known as a Serial Communications Interface or SCI.) The EUSART can be configured as a full-duplex asynchronous system that can communicate with peripheral devices, such as CRT terminals and personal computers.
PIC18F87J10 FAMILY REGISTER 20-1: R/W-0 CSRC TXSTAx: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0 TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care.
PIC18F87J10 FAMILY REGISTER 20-2: RCSTAx: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RXx/DTx and TXx/CKx pins as serial port pins) 0 = Serial port disabled (held in Reset) b
PIC18F87J10 FAMILY REGISTER 20-3: BAUDCONx: BAUD RATE CONTROL REGISTER R/W-0 R-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ABDOVF: Auto-Baud Acquisition Rollover Status bit 1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software) 0 = No BRG rollov
PIC18F87J10 FAMILY 20.1 Baud Rate Generator (BRG) The BRG is a dedicated 8-bit or 16-bit generator that supports both the Asynchronous and Synchronous modes of the EUSART. By default, the BRG operates in 8-bit mode; setting the BRG16 bit (BAUDCONx<3>) selects 16-bit mode. The SPBRGHx:SPBRGx register pair controls the period of a free-running timer. In Asynchronous mode, bits BRGH (TXSTAx<2>) and BRG16 (BAUDCONx<3>) also control the baud rate. In Synchronous mode, BRGH is ignored.
PIC18F87J10 FAMILY EXAMPLE 20-1: CALCULATING BAUD RATE ERROR For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: Desired Baud Rate = FOSC/(64 ([SPBRGHx:SPBRGx] + 1)) Solving for SPBRGHx:SPBRGx: X = ((FOSC/Desired Baud Rate)/64) – 1 = ((16000000/9600)/64) – 1 = [25.042] = 25 Calculated Baud Rate = 16000000/(64 (25 + 1)) = 9615 Error = (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate = (9615 – 9600)/9600 = 0.
PIC18F87J10 FAMILY TABLE 20-3: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE (K) FOSC = 40.000 MHz FOSC = 20.000 MHz Actual Rate (K) FOSC = 10.000 MHz Actual Rate (K) FOSC = 8.000 MHz Actual Rate (K) Actual Rate (K) % Error 0.3 — — — — — — — — — — — — 1.2 — — — 1.221 1.73 255 1.202 0.16 129 1.201 -0.16 103 2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 2.403 -0.16 51 9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9.
PIC18F87J10 FAMILY TABLE 20-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE (K) FOSC = 40.000 MHz FOSC = 20.000 MHz (decimal) Actual Rate (K) % Error 0.00 0.02 8332 2082 0.300 1.200 0.06 1040 2.399 Actual Rate (K) % Error 0.3 1.2 0.300 1.200 2.4 2.402 SPBRG Value FOSC = 10.000 MHz (decimal) Actual Rate (K) % Error 0.02 -0.03 4165 1041 0.300 1.200 -0.03 520 2.404 SPBRG Value FOSC = 8.000 MHz (decimal) Actual Rate (K) % Error 0.
PIC18F87J10 FAMILY 20.1.3 AUTO-BAUD RATE DETECT The Enhanced USART module supports the automatic detection and calibration of baud rate. This feature is active only in Asynchronous mode and while the WUE bit is clear. Note 1: If the WUE bit is set with the ABDEN bit, Auto-Baud Rate Detection will occur on the byte following the Break character. 2: It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG clock source.
PIC18F87J10 FAMILY FIGURE 20-1: BRG Value AUTOMATIC BAUD RATE CALCULATION XXXXh RXx pin 0000h 001Ch Start Edge #1 Bit 1 Bit 0 Edge #2 Bit 3 Bit 2 Edge #3 Bit 5 Bit 4 Edge #4 Bit 7 Bit 6 Edge #5 Stop Bit BRG Clock Auto-Cleared Set by User ABDEN bit RCxIF bit (Interrupt) Read RCREGx SPBRGx XXXXh 1Ch SPBRGHx XXXXh 00h Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.
PIC18F87J10 FAMILY 20.2 EUSART Asynchronous Mode Once the TXREGx register transfers the data to the TSR register (occurs in one TCY), the TXREGx register is empty and the TXxIF flag bit is set. This interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TXxIE. TXxIF will be set regardless of the state of TXxIE; it cannot be cleared in software.
PIC18F87J10 FAMILY FIGURE 20-4: ASYNCHRONOUS TRANSMISSION Write to TXREGx Word 1 BRG Output (Shift Clock) TXx (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXxIF bit (Transmit Buffer Reg. Empty Flag) 1 TCY Word 1 Transmit Shift Reg TRMT bit (Transmit Shift Reg. Empty Flag) FIGURE 20-5: ASYNCHRONOUS TRANSMISSION (BACK TO BACK) Write to TXREGx Word 2 Word 1 BRG Output (Shift Clock) TXx (pin) Start bit bit 0 bit 1 1 TCY TXxIF bit (Interrupt Reg.
PIC18F87J10 FAMILY 20.2.2 EUSART ASYNCHRONOUS RECEIVER 20.2.3 The receiver block diagram is shown in Figure 20-6. The data is received on the RXx pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. This mode would typically be used in RS-232 systems. This mode would typically be used in RS-485 systems.
PIC18F87J10 FAMILY FIGURE 20-7: ASYNCHRONOUS RECEPTION Start bit RXx (pin) bit 0 bit 7/8 Stop bit bit 1 Rcv Shift Reg Rcv Buffer Reg Start bit bit 0 Stop bit Start bit bit 7/8 Stop bit Word 2 RCREGx Word 1 RCREGx Read Rcv Buffer Reg RCREGx bit 7/8 RCxIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RXx input. The RCREGx (Receive Buffer) is read after the third word causing the OERR (Overrun) bit to be set.
PIC18F87J10 FAMILY 20.2.4.1 Special Considerations Using Auto-Wake-up 20.2.4.2 Since auto-wake-up functions by sensing rising edge transitions on RXx/DTx, information with any state changes before the Stop bit may signal a false end-of-character and cause data or framing errors. To work properly, therefore, the initial character in the transmission must be all ‘0’s. This can be 00h (8 bytes) for standard RS-232 devices or 000h (12 bits) for LIN bus.
PIC18F87J10 FAMILY 20.2.5 BREAK CHARACTER SEQUENCE The EUSART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. The Break character transmit consists of a Start bit, followed by twelve ‘0’ bits and a Stop bit. The Frame Break character is sent whenever the SENDB and TXEN bits (TXSTAx<3> and TXSTAx<5>) are set while the Transmit Shift Register is loaded with data.
PIC18F87J10 FAMILY 20.3 EUSART Synchronous Master Mode Once the TXREGx register transfers the data to the TSR register (occurs in one TCY), the TXREGx is empty and the TXxIF flag bit is set. The interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TXxIE. TXxIF is set regardless of the state of enable bit, TXxIE; it cannot be cleared in software. It will reset only when new data is loaded into the TXREGx register.
PIC18F87J10 FAMILY FIGURE 20-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX1/DT1 pin bit 0 bit 1 bit 2 bit 6 bit 7 RC6/TX1/CK1 pin Write to TXREG1 reg TX1IF bit TRMT bit TXEN bit Note: This example is equally applicable to EUSART2 (RG1/TX2/CK2 and RG2/RX2/DT2).
PIC18F87J10 FAMILY 20.3.2 EUSART SYNCHRONOUS MASTER RECEPTION Once Synchronous mode is selected, reception is enabled by setting either the Single Receive Enable bit, SREN (RCSTAx<5>), or the Continuous Receive Enable bit, CREN (RCSTAx<4>). Data is sampled on the RXx pin on the falling edge of the clock. If enable bit, SREN, is set, only a single word is received. If enable bit, CREN, is set, the reception is continuous until CREN is cleared. If both bits are set, then CREN takes precedence.
PIC18F87J10 FAMILY 20.4 EUSART Synchronous Slave Mode To set up a Synchronous Slave Transmission: 1. Synchronous Slave mode is entered by clearing bit, CSRC (TXSTAx<7>). This mode differs from the Synchronous Master mode in that the shift clock is supplied externally at the CKx pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in any low-power mode. 20.4.1 2. 3. 4. 5. EUSART SYNCHRONOUS SLAVE TRANSMISSION 6.
PIC18F87J10 FAMILY 20.4.2 EUSART SYNCHRONOUS SLAVE RECEPTION To set up a Synchronous Slave Reception: 1. The operation of the Synchronous Master and Slave modes is identical, except in the case of Sleep, or any Idle mode and bit, SREN, which is a “don’t care” in Slave mode. If receive is enabled by setting the CREN bit prior to entering Sleep or any Idle mode, then a word may be received while in this low-power mode.
PIC18F87J10 FAMILY NOTES: DS39663F-page 260 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 21.0 10-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The Analog-to-Digital (A/D) Converter module has 11 inputs for the 64-pin devices and 15 for the 80-pin devices. This module allows conversion of an analog input signal to a corresponding 10-bit digital number.
PIC18F87J10 FAMILY REGISTER 21-2: ADCON1: A/D CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared AN8 AN7 AN6 AN4 AN3 AN2 AN1 AN0 PCFG<3:0>: A/D Port Configuration Control bits: AN9 bit 3-0 AN10 VCFG0: Voltage Reference Configuration bit (VREF+ source) 1 = VREF+ (AN3) 0 = AVDD
PIC18F87J10 FAMILY REGISTER 21-3: ADCON2: A/D CONTROL REGISTER 2 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as ‘0’ bit 5-3 ACQT<2:0>: A/D Acquisition Time Select bits 111 = 20 TAD 110
PIC18F87J10 FAMILY The analog reference voltage is software selectable to either the device’s positive and negative supply voltage (AVDD and AVSS), or the voltage level on the RA3/AN3/VREF+ and RA2/AN2/VREF- pins. the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRESH:ADRESL register pair, the GO/DONE bit (ADCON0<1>) is cleared and A/D Interrupt Flag bit, ADIF, is set. The A/D Converter has a unique feature of being able to operate while the device is in Sleep mode.
PIC18F87J10 FAMILY After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section 21.1 “A/D Acquisition Requirements”. After this acquisition time has elapsed, the A/D conversion can be started. An acquisition time can be programmed to occur between setting the GO/DONE bit and the actual start of the conversion.
PIC18F87J10 FAMILY 21.1 A/D Acquisition Requirements For the A/D Converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 21-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor, CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD).
PIC18F87J10 FAMILY 21.2 Selecting and Configuring Automatic Acquisition Time The ADCON2 register allows the user to select an acquisition time that occurs each time the GO/DONE bit is set. When the GO/DONE bit is set, sampling is stopped and a conversion begins. The user is responsible for ensuring the required acquisition time has passed between selecting the desired input channel and setting the GO/DONE bit.
PIC18F87J10 FAMILY 21.5 A/D Conversions 21.6 Figure 21-3 shows the operation of the A/D Converter after the GO/DONE bit has been set and the ACQT<2:0> bits are cleared. A conversion is started after the following instruction to allow entry into Sleep mode before the conversion begins. An A/D conversion can be started by the “Special Event Trigger” of the ECCP2 module. This requires that the CCP2M<3:0> bits (CCP2CON<3:0>) be programmed as ‘1011’ and that the A/D module is enabled (ADON bit is set).
PIC18F87J10 FAMILY 21.7 A/D Converter Calibration If the A/D is expected to operate while the device is in a power-managed mode, the ACQT<2:0> and ADCS<2:0> bits in ADCON2 should be updated in accordance with the power-managed mode clock that will be used. After the power-managed mode is entered (either of the power-managed Run modes), an A/D acquisition or conversion may be started.
PIC18F87J10 FAMILY NOTES: DS39663F-page 270 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 22.0 COMPARATOR MODULE The analog comparator module contains two comparators that can be configured in a variety of ways. The inputs can be selected from the analog inputs multiplexed with pins RF1 through RF6, as well as the on-chip voltage reference (see Section 23.0 “Comparator Voltage Reference Module”). The digital outputs (normal or inverted) are available at the pin level and can also be read through the control register.
PIC18F87J10 FAMILY 22.1 Comparator Configuration There are eight modes of operation for the comparators, shown in Figure 22-1. Bits, CM<2:0>, of the CMCON register are used to select these modes. The TRISF register controls the data direction of the comparator pins for each mode.
PIC18F87J10 FAMILY 22.2 Comparator Operation 22.3.2 A single comparator is shown in Figure 22-2, along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input VIN-, the output of the comparator is a digital low level. When the analog input at VIN+ is greater than the analog input VIN-, the output of the comparator is a digital high level.
PIC18F87J10 FAMILY + To RF1 or RF2 Pin - Port Pins COMPARATOR OUTPUT BLOCK DIAGRAM MULTIPLEX FIGURE 22-3: D Q Bus Data CxINV Read CMCON EN D Q EN CL From Other Comparator Reset 22.6 Comparator Interrupts The comparator interrupt flag is set whenever there is a change in the output value of either comparator. Software will need to maintain information about the status of the output bits, as read from CMCON<7:6>, to determine the actual change that occurred.
PIC18F87J10 FAMILY 22.9 Analog Input Connection Considerations range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up condition may occur. A maximum source impedance of 10 kΩ is recommended for the analog sources. Any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current. A simplified circuit for an analog input is shown in Figure 22-4.
PIC18F87J10 FAMILY NOTES: DS39663F-page 276 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 23.0 COMPARATOR VOLTAGE REFERENCE MODULE The comparator voltage reference is a 16-tap resistor ladder network that provides a selectable reference voltage. Although its primary purpose is to provide a reference for the analog comparators, it may also be used independently of them. A block diagram of the module is shown in Figure 23-1.
PIC18F87J10 FAMILY FIGURE 23-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM VREF+ VDD CVRSS = 1 8R CVRSS = 0 CVR<3:0> R CVREN R R 16-to-1 MUX R 16 Steps R CVREF R R CVRR VREF- 8R CVRSS = 1 CVRSS = 0 23.2 Voltage Reference Accuracy/Error The full range of voltage reference cannot be realized due to the construction of the module. The transistors on the top and bottom of the resistor ladder network (Figure 23-1) keep CVREF from approaching the reference source rails.
PIC18F87J10 FAMILY FIGURE 23-2: COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC18F87J10 CVREF Module R(1) Voltage Reference Output Impedance Note 1: TABLE 23-1: Name CVRCON + – RF5 CVREF Output R is dependent upon the comparator voltage reference Configuration bits, CVRCON<5> and CVRCON<3:0>.
PIC18F87J10 FAMILY NOTES: DS39663F-page 280 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 24.0 SPECIAL FEATURES OF THE CPU PIC18F87J10 family devices include several features intended to maximize reliability and minimize cost through elimination of external components.
PIC18F87J10 FAMILY TABLE 24-2: CONFIGURATION BITS AND DEVICE IDs File Name 300000h CONFIG1L Default/ Unprogrammed Value(1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DEBUG XINST STVREN — — — — WDTEN 111- ---1 ---- 01-- (2) (2) (2) (2) (3) 300001h CONFIG1H — CP0 — — 300002h CONFIG2L IESO FCMEN — — — FOSC2 FOSC1 FOSC0 11-- -111 300003h CONFIG2H —(2) —(2) —(2) —(2) WDTPS3 WDTPS2 WDTPS1 WDTPS0 ---- 1111 300004h CONFIG3L WAIT(4) BW(4) EMB1(4) — —
PIC18F87J10 FAMILY REGISTER 24-1: CONFIG1L: CONFIGURATION REGISTER 1 LOW (BYTE ADDRESS 300000h) R/WO-1 R/WO-1 R/WO-1 U-0 U-0 U-0 U-0 R/WO-1 DEBUG XINST STVREN — — — — WDTEN bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 DEBUG: Background Debugger Enable bit 1 = Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins 0 = Background
PIC18F87J10 FAMILY REGISTER 24-3: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h) R/WO-1 R/WO-1 U-0 U-0 U-0 R/WO-1 R/WO-1 R/WO-1 IESO FCMEN — — — FOSC2 FOSC1 FOSC0 bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 IESO: Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit 1 = Two-Speed Start-up enabled 0 = Two-Speed Start-up
PIC18F87J10 FAMILY REGISTER 24-5: R/WO-1 CONFIG3L: CONFIGURATION REGISTER 3 LOW (BYTE ADDRESS 300004h) R/WO-1 (1) WAIT BW (1) R/WO-1 R/WO-1 (1) (1) EMB1 EMB0 R/WO-1 EASHFT (1) U-0 U-0 U-0 — — — bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 WAIT: External Bus Wait Enable bit(1) 1 = Wait states for operations on external memory bus disabled 0 = Wait stat
PIC18F87J10 FAMILY REGISTER 24-7: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F87J10 FAMILY DEVICES R R R R R R R R DEV2(1) DEV1(1) DEV0(1) REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Read-only bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7-5 DEV<2:0>: Device ID bits(1) 111 = PIC18F85J10 101 = PIC18F67J10 100 = PIC18F66J15 011 = PIC18F66J10 or PIC18F87J10 010 = PIC18F65J15 or PIC18F86J15 001 = PIC18F65J10 or PIC
PIC18F87J10 FAMILY 24.2 Watchdog Timer (WDT) Note 1: The CLRWDT and SLEEP instructions clear the WDT and postscaler counts when executed. For PIC18F87J10 family devices, the WDT is driven by the INTRC oscillator. When the WDT is enabled, the clock source is also enabled. The nominal WDT period is 4 ms and has the same stability as the INTRC oscillator. The 4 ms period of the WDT is multiplied by a 16-bit postscaler.
PIC18F87J10 FAMILY 24.3 On-Chip Voltage Regulator All of the PIC18F87J10 family devices power their core digital logic at a nominal 2.5V. For designs that are required to operate at a higher typical voltage, such as 3.3V, all devices in the PIC18F87J10 family incorporate an on-chip regulator that allows the device to run its core logic from VDD. The regulator is controlled by the ENVREG pin. Tying VDD to the pin enables the regulator, which in turn, provides power to the core from the other VDD pins.
PIC18F87J10 FAMILY 24.4 Two-Speed Start-up In all other power-managed modes, Two-Speed Start-up is not used. The device will be clocked by the currently selected clock source until the primary clock source becomes available. The setting of the IESO bit is ignored. The Two-Speed Start-up feature helps to minimize the latency period, from oscillator start-up to code execution, by allowing the microcontroller to use the INTRC oscillator as a clock source until the primary clock source is available.
PIC18F87J10 FAMILY 24.5 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) allows the microcontroller to continue operation in the event of an external oscillator failure by automatically switching the device clock to the internal oscillator block. The FSCM function is enabled by setting the FCMEN Configuration bit. When FSCM is enabled, the INTRC oscillator runs at all times to monitor clocks to peripherals and provide a backup clock in the event of a clock failure.
PIC18F87J10 FAMILY FIGURE 24-5: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure Device Clock Output CM Output (Q) Failure Detected OSCFIF CM Test Note: 24.5.3 CM Test CM Test The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. FSCM INTERRUPTS IN POWER-MANAGED MODES By entering a power-managed mode, the clock multiplexor selects the clock source selected by the OSCCON register.
PIC18F87J10 FAMILY 24.6 Program Verification and Code Protection For all devices in the PIC18F87J10 family of devices, the on-chip program memory space is treated as a single block. Code protection for this block is controlled by one Configuration bit, CP0. This bit inhibits external reads and writes to the program memory space. It has no direct effect in normal execution mode. 24.6.
PIC18F87J10 FAMILY 25.0 INSTRUCTION SET SUMMARY The PIC18F87J10 family of devices incorporate the standard set of 75 PIC18 core instructions, as well as an extended set of 8 new instructions for the optimization of code that is recursive or that utilizes a software stack. The extended set is discussed later in this section. 25.
PIC18F87J10 FAMILY TABLE 25-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit: a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank. C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative.
PIC18F87J10 FAMILY FIGURE 25-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 15 10 9 OPCODE Example Instruction 8 7 d 0 a ADDWF MYREG, W, B f (FILE #) d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 0 OPCODE 15 f (Source FILE #) 12 11 MOVFF MYREG1, MYREG2 0 f (Destination FILE
PIC18F87J10 FAMILY TABLE 25-2: PIC18F87J10 FAMILY INSTRUCTION SET Mnemonic, Operands Description Cycles 16-bit Instruction Word MSb LSb Status Affected Notes BYTE-ORIENTED OPERATIONS ADDWF ADDWFC ANDWF CLRF COMF CPFSEQ CPFSGT CPFSLT DECF DECFSZ DCFSNZ INCF INCFSZ INFSNZ IORWF MOVF MOVFF f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a fs, fd MOVWF MULWF NEGF RLCF RLNCF RRCF RRNCF SETF SUBFWB f, a f, a f, a f, d, a f, d, a f, d, a
PIC18F87J10 FAMILY TABLE 25-2: PIC18F87J10 FAMILY INSTRUCTION SET (CONTINUED) Mnemonic, Operands Description Cycles 16-bit Instruction Word MSb LSb Status Affected Notes BIT-ORIENTED OPERATIONS BCF BSF BTFSC BTFSS BTG f, b, a f, b, a f, b, a f, b, a f, b, a Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Bit Toggle f 1 1 1 (2 or 3) 1 (2 or 3) 1 1001 1000 1011 1010 0111 bbba bbba bbba bbba bbba ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff None None None None None
PIC18F87J10 FAMILY TABLE 25-2: PIC18F87J10 FAMILY INSTRUCTION SET (CONTINUED) Mnemonic, Operands Description Cycles 16-bit Instruction Word MSb LSb Status Affected Notes LITERAL OPERATIONS ADDLW ANDLW IORLW LFSR k k k f, k MOVLB MOVLW MULLW RETLW SUBLW XORLW k k k k k k Add Literal and WREG AND Literal with WREG Inclusive OR Literal with WREG Move Literal (12-bit) 2nd word to FSR(f) 1st word Move Literal to BSR<3:0> Move Literal to WREG Multiply Literal with WREG Return with Literal in WREG Sub
PIC18F87J10 FAMILY 25.1.1 STANDARD INSTRUCTION SET ADDLW ADD Literal to W ADDWF ADD W to f Syntax: ADDLW Syntax: ADDWF Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) + (f) → dest Status Affected: N, OV, C, DC, Z k Operands: 0 ≤ k ≤ 255 Operation: (W) + k → W Status Affected: N, OV, C, DC, Z Encoding: 0000 1111 kkkk kkkk Description: The contents of W are added to the 8-bit literal ‘k’ and the result is placed in W.
PIC18F87J10 FAMILY ADDWFC ADD W and Carry bit to f ANDLW AND Literal with W Syntax: ADDWFC Syntax: ANDLW Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] f {,d {,a}} Operation: (W) + (f) + (C) → dest Status Affected: N,OV, C, DC, Z Encoding: 0010 Description: 00da ffff Add W, the Carry flag and data memory location, ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in data memory location ‘f’. If ‘a’ is ‘0’, the Access Bank is selected.
PIC18F87J10 FAMILY ANDWF AND W with f BC Branch if Carry Syntax: ANDWF Syntax: BC Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] f {,d {,a}} Operation: (W) .AND. (f) → dest Status Affected: N, Z Encoding: 0001 Description: Operands: -128 ≤ n ≤ 127 Operation: if Carry bit is ‘1’, (PC) + 2 + 2n → PC Status Affected: None Encoding: 01da ffff ffff 1110 Description: The contents of W are ANDed with register ‘f’. If ‘d’ is ‘0’, the result is stored in W.
PIC18F87J10 FAMILY BCF Bit Clear f BN Branch if Negative Syntax: BCF Syntax: BN Operands: 0 ≤ f ≤ 255 0≤b≤7 a ∈ [0,1] f, b {,a} Operation: 0 → f Status Affected: None Encoding: 1001 Description: Operands: -128 ≤ n ≤ 127 Operation: if Negative bit is ‘1’, (PC) + 2 + 2n → PC Status Affected: None Encoding: bbba ffff ffff 1110 Description: Bit ‘b’ in register ‘f’ is cleared. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank.
PIC18F87J10 FAMILY BNC Branch if Not Carry BNN Branch if Not Negative Syntax: BNC Syntax: BNN n n Operands: -128 ≤ n ≤ 127 Operands: -128 ≤ n ≤ 127 Operation: if Carry bit is ‘0’, (PC) + 2 + 2n → PC Operation: if Negative bit is ‘0’, (PC) + 2 + 2n → PC Status Affected: None Status Affected: None Encoding: 1110 Description: 0011 nnnn nnnn If the Carry bit is ‘0’, then the program will branch. Encoding: 1110 Description: The 2’s complement number ‘2n’ is added to the PC.
PIC18F87J10 FAMILY BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: BNOV Syntax: BNZ n n Operands: -128 ≤ n ≤ 127 Operands: -128 ≤ n ≤ 127 Operation: if Overflow bit is ‘0’, (PC) + 2 + 2n → PC Operation: if Zero bit is ‘0’, (PC) + 2 + 2n → PC Status Affected: None Status Affected: None Encoding: 1110 Description: 0101 nnnn nnnn If the Overflow bit is ‘0’, then the program will branch. Encoding: 1110 Description: The 2’s complement number ‘2n’ is added to the PC.
PIC18F87J10 FAMILY BRA Unconditional Branch BSF Bit Set f Syntax: BRA Syntax: BSF Operands: -1024 ≤ n ≤ 1023 Operands: Operation: (PC) + 2 + 2n → PC Status Affected: None 0 ≤ f ≤ 255 0≤b≤7 a ∈ [0,1] Operation: 1 → f Status Affected: None Encoding: n 1101 Description: 0nnn nnnn nnnn Add the 2’s complement number ‘2n’ to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a two-cycle instruction.
PIC18F87J10 FAMILY BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set Syntax: BTFSC f, b {,a} Syntax: BTFSS f, b {,a} Operands: 0 ≤ f ≤ 255 0≤b≤7 a ∈ [0,1] Operands: 0 ≤ f ≤ 255 0≤b<7 a ∈ [0,1] Operation: skip if (f) = 0 Operation: skip if (f) = 1 Status Affected: None Status Affected: None Encoding: 1011 Description: bbba ffff ffff If bit ‘b’ in register ‘f’ is ‘0’, then the next instruction is skipped.
PIC18F87J10 FAMILY BTG Bit Toggle f BOV Branch if Overflow Syntax: BTG f, b {,a} Syntax: BOV Operands: 0 ≤ f ≤ 255 0≤b<7 a ∈ [0,1] Operands: -128 ≤ n ≤ 127 Operation: if Overflow bit is ‘1’, (PC) + 2 + 2n → PC Status Affected: None Operation: (f) → f Status Affected: None Encoding: 0111 Description: Encoding: bbba ffff ffff 1110 Description: Bit ‘b’ in data memory location ‘f’ is inverted.
PIC18F87J10 FAMILY BZ Branch if Zero CALL Subroutine Call Syntax: BZ Syntax: CALL k {,s} n Operands: -128 ≤ n ≤ 127 Operands: Operation: if Zero bit is ‘1’, (PC) + 2 + 2n → PC 0 ≤ k ≤ 1048575 s ∈ [0,1] Operation: Status Affected: None (PC) + 4 → TOS, k → PC<20:1>; if s = 1, (W) → WS, (STATUS) → STATUSS, (BSR) → BSRS Status Affected: None Encoding: 1110 Description: 0000 nnnn nnnn If the Zero bit is ‘1’, then the program will branch.
PIC18F87J10 FAMILY CLRF Clear f Syntax: CLRF Operands: 0 ≤ f ≤ 255 a ∈ [0,1] f {,a} Operation: 000h → f, 1→Z Status Affected: Z Encoding: 0110 Description: 101a ffff ffff Clears the contents of the specified register.
PIC18F87J10 FAMILY COMF Complement f CPFSEQ Compare f with W, Skip if f = W Syntax: COMF Syntax: CPFSEQ Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (f) – (W), skip if (f) = (W) (unsigned comparison) Status Affected: None f {,d {,a}} Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: f → dest Status Affected: N, Z Encoding: 0001 Description: 11da ffff ffff The contents of register ‘f’ are complemented. If ‘d’ is ‘0’, the result is stored in W.
PIC18F87J10 FAMILY CPFSGT Compare f with W, Skip if f > W CPFSLT Compare f with W, Skip if f < W Syntax: CPFSGT Syntax: CPFSLT Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (f) – (W), skip if (f) > (W) (unsigned comparison) Operation: (f) – (W), skip if (f) < (W) (unsigned comparison) Status Affected: None Status Affected: None Encoding: Description: 0110 f {,a} 010a ffff ffff Compares the contents of data memory location ‘f’ to the contents of the W by
PIC18F87J10 FAMILY DAW Decimal Adjust W Register DECF Decrement f Syntax: DAW Syntax: DECF f {,d {,a}} Operands: None Operands: Operation: If [W<3:0> > 9] or [DC = 1] then, (W<3:0>) + 6 → W<3:0>; else, (W<3:0>) → W<3:0>; 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – 1 → dest Status Affected: C, DC, N, OV, Z Encoding: If [W<7:4> > 9] or [C = 1] then, (W<7:4>) + 6 → W<7:4>; C = 1, else, (W<7:4>) → W<7:4> Status Affected: 0000 Description: 0000 0000 0000 0111 Description: DAW adju
PIC18F87J10 FAMILY DECFSZ Decrement f, Skip if 0 DCFSNZ Decrement f, Skip if not 0 Syntax: DECFSZ f {,d {,a}} Syntax: DCFSNZ Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – 1 → dest, skip if result = 0 Operation: (f) – 1 → dest, skip if result ≠ 0 Status Affected: None Status Affected: None Encoding: 0010 Description: 11da ffff ffff The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in W.
PIC18F87J10 FAMILY GOTO Unconditional Branch INCF Increment f Syntax: GOTO k Syntax: INCF Operands: 0 ≤ k ≤ 1048575 Operands: Operation: k → PC<20:1> Status Affected: None 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) + 1 → dest Status Affected: C, DC, N, OV, Z Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 1111 k19kkk k7kkk kkkk kkkk0 kkkk8 Description: GOTO allows an unconditional branch anywhere within entire 2-Mbyte memory range.
PIC18F87J10 FAMILY INCFSZ Increment f, Skip if 0 INFSNZ Syntax: INCFSZ Syntax: INFSNZ 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] f {,d {,a}} Increment f, Skip if not 0 f {,d {,a}} Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: Operation: (f) + 1 → dest, skip if result = 0 Operation: (f) + 1 → dest, skip if result ≠ 0 Status Affected: None Status Affected: None Encoding: 0011 Description: 11da ffff ffff The contents of register ‘f’ are incremented.
PIC18F87J10 FAMILY IORLW Inclusive OR Literal with W IORWF Inclusive OR W with f Syntax: IORLW k Syntax: IORWF Operands: 0 ≤ k ≤ 255 Operands: Operation: (W) .OR. k → W Status Affected: N, Z 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) .OR. (f) → dest Status Affected: N, Z Encoding: 0000 1001 kkkk kkkk Description: The contents of W are ORed with the eight-bit literal ‘k’. The result is placed in W.
PIC18F87J10 FAMILY LFSR Load FSR MOVF Move f Syntax: LFSR f, k Syntax: MOVF Operands: 0≤f≤2 0 ≤ k ≤ 4095 Operands: Operation: k → FSRf 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Status Affected: None Operation: f → dest Status Affected: N, Z Encoding: 1110 1111 1110 0000 00ff k7kkk k11kkk kkkk Description: The 12-bit literal ‘k’ is loaded into the file select register pointed to by ‘f’.
PIC18F87J10 FAMILY MOVFF Move f to f MOVLB Move Literal to Low Nibble in BSR Syntax: MOVFF fs,fd Syntax: MOVLW k Operands: 0 ≤ fs ≤ 4095 0 ≤ fd ≤ 4095 Operands: 0 ≤ k ≤ 255 Operation: k → BSR Status Affected: None Operation: (fs) → fd Status Affected: None Encoding: 1st word (source) 2nd word (destin.) Encoding: 1100 1111 Description: ffff ffff ffff ffff ffffs ffffd The contents of source register ‘fs’ are moved to destination register ‘fd’.
PIC18F87J10 FAMILY MOVLW Move Literal to W MOVWF Move W to f Syntax: MOVLW k Syntax: MOVWF Operands: 0 ≤ k ≤ 255 Operands: Operation: k→W 0 ≤ f ≤ 255 a ∈ [0,1] Status Affected: None Encoding: 0000 Description: 1110 kkkk kkkk The eight-bit literal ‘k’ is loaded into W.
PIC18F87J10 FAMILY MULLW Multiply Literal with W MULWF Syntax: MULLW Syntax: MULWF Operands: 0 ≤ k ≤ 255 Operands: Operation: (W) x k → PRODH:PRODL 0 ≤ f ≤ 255 a ∈ [0,1] Status Affected: None Operation: (W) x (f) → PRODH:PRODL Status Affected: None Encoding: 0000 Description: k 1101 kkkk kkkk An unsigned multiplication is carried out between the contents of W and the 8-bit literal ‘k’. The 16-bit result is placed in PRODH:PRODL register pair. PRODH contains the high byte.
PIC18F87J10 FAMILY NEGF Negate f Syntax: NEGF Operands: 0 ≤ f ≤ 255 a ∈ [0,1] f {,a} Operation: (f) + 1 → f Status Affected: N, OV, C, DC, Z Encoding: 0110 Description: 110a ffff If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details.
PIC18F87J10 FAMILY POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: POP Syntax: PUSH Operands: None Operands: None Operation: (TOS) → bit bucket Operation: (PC + 2) → TOS Status Affected: None Status Affected: None Encoding: 0000 0000 0000 0110 Encoding: 0000 0000 0000 0101 Description: The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack.
PIC18F87J10 FAMILY RCALL Relative Call RESET Reset Syntax: RCALL Syntax: RESET n Operands: -1024 ≤ n ≤ 1023 Operands: None Operation: (PC) + 2 → TOS, (PC) + 2 + 2n → PC Operation: Reset all registers and flags that are affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: 1101 Description: 1nnn nnnn nnnn Subroutine call with a jump up to 1K from the current location. First, return address (PC + 2) is pushed onto the stack.
PIC18F87J10 FAMILY RETFIE Return from Interrupt RETLW Return Literal to W Syntax: RETFIE {s} Syntax: RETLW k Operands: s ∈ [0,1] Operands: 0 ≤ k ≤ 255 Operation: (TOS) → PC, 1 → GIE/GIEH or PEIE/GIEL; if s = 1, (WS) → W, (STATUSS) → STATUS, (BSRS) → BSR, PCLATU, PCLATH are unchanged Operation: k → W, (TOS) → PC, PCLATU, PCLATH are unchanged Status Affected: None Status Affected: 0000 0000 0001 1 Cycles: 2 Q Cycle Activity: Q2 Q3 Q4 Decode No operation No operation POP PC from
PIC18F87J10 FAMILY RETURN Return from Subroutine RLCF Rotate Left f through Carry Syntax: RETURN {s} Syntax: RLCF Operands: s ∈ [0,1] Operands: Operation: (TOS) → PC; if s = 1, (WS) → W, (STATUSS) → STATUS, (BSRS) → BSR, PCLATU, PCLATH are unchanged 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) → dest, (f<7>) → C, (C) → dest<0> Status Affected: C, N, Z Status Affected: None Encoding: 0000 Description: Encoding: 0000 0001 001s 0011 Description: Return from subroutine.
PIC18F87J10 FAMILY RLNCF Rotate Left f (No Carry) RRCF Rotate Right f through Carry Syntax: RLNCF Syntax: RRCF Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) → dest, (f<7>) → dest<0> Operation: Status Affected: N, Z (f) → dest, (f<0>) → C, (C) → dest<7> Status Affected: C, N, Z Encoding: 0100 Description: f {,d {,a}} 01da ffff ffff The contents of register ‘f’ are rotated one bit to the left.
PIC18F87J10 FAMILY RRNCF Rotate Right f (No Carry) SETF Set f Syntax: RRNCF Syntax: SETF Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (f) → dest, (f<0>) → dest<7> Status Affected: N, Z Encoding: 0100 Description: f {,d {,a}} 00da Operation: FFh → f Status Affected: None Encoding: ffff ffff 0110 Description: The contents of register ‘f’ are rotated one bit to the right. If ‘d’ is ‘0’, the result is placed in W.
PIC18F87J10 FAMILY SLEEP Enter Sleep Mode SUBFWB Subtract f from W with Borrow Syntax: SLEEP Syntax: SUBFWB Operands: None Operands: Operation: 00h → WDT, 0 → WDT postscaler, 1 → TO, 0 → PD 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) – (f) – (C) → dest Status Affected: N, OV, C, DC, Z Status Affected: TO, PD Encoding: 0000 Description: Encoding: 0000 0000 0011 0101 Description: The Power-Down status bit (PD) is cleared. The Time-out status bit (TO) is set.
PIC18F87J10 FAMILY SUBLW Subtract W from Literal SUBWF Subtract W from f Syntax: SUBLW k Syntax: SUBWF Operands: 0 ≤ k ≤ 255 Operands: Operation: k – (W) → W Status Affected: N, OV, C, DC, Z 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – (W) → dest Status Affected: N, OV, C, DC, Z Encoding: 0000 1000 kkkk kkkk Description: W is subtracted from the eight-bit literal ‘k’. The result is placed in W.
PIC18F87J10 FAMILY SUBWFB Subtract W from f with Borrow SWAPF Swap f Syntax: SUBWFB Syntax: SWAPF f {,d {,a}} Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – (W) – (C) → dest Operation: Status Affected: N, OV, C, DC, Z (f<3:0>) → dest<7:4>, (f<7:4>) → dest<3:0> Status Affected: None Encoding: 0101 Description: f {,d {,a}} 10da ffff ffff Subtract W and the Carry flag (borrow) from register ‘f’ (2’s complement method).
PIC18F87J10 FAMILY TBLRD Table Read TBLRD Table Read (Continued) Syntax: TBLRD ( *; *+; *-; +*) Example 1: TBLRD Operands: None Operation: if TBLRD *, (Prog Mem (TBLPTR)) → TABLAT, TBLPTR – No Change; if TBLRD *+, (Prog Mem (TBLPTR)) → TABLAT, (TBLPTR) + 1 → TBLPTR; if TBLRD *-, (Prog Mem (TBLPTR)) → TABLAT, (TBLPTR) – 1 → TBLPTR; if TBLRD +*, (TBLPTR) + 1 → TBLPTR, (Prog Mem (TBLPTR)) → TABLAT Before Instruction TABLAT TBLPTR MEMORY(00A356h) After Instruction TABLAT TBLPTR Example 2: Status Af
PIC18F87J10 FAMILY TBLWT Table Write TBLWT Table Write (Continued) Syntax: TBLWT ( *; *+; *-; +*) Example 1: TBLWT *+; Operands: None Operation: if TBLWT*, (TABLAT) → Holding Register, TBLPTR – No Change; if TBLWT*+, (TABLAT) → Holding Register, (TBLPTR) + 1 → TBLPTR; if TBLWT*-, (TABLAT) → Holding Register, (TBLPTR) – 1 → TBLPTR; if TBLWT+*, (TBLPTR) + 1 → TBLPTR, (TABLAT) → Holding Register Status Affected: Example 2: None Encoding: Description: Before Instruction TABLAT = 55h TBLPTR = 00
PIC18F87J10 FAMILY TSTFSZ Test f, Skip if 0 XORLW Exclusive OR Literal with W Syntax: TSTFSZ f {,a} Syntax: XORLW k Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operands: 0 ≤ k ≤ 255 Operation: (W) .XOR. k → W Status Affected: N, Z Operation: skip if f = 0 Status Affected: None Encoding: Encoding: 0110 Description: 011a ffff ffff If ‘f’ = 0, the next instruction fetched during the current instruction execution is discarded and a NOP is executed, making this a two-cycle instruction.
PIC18F87J10 FAMILY XORWF Exclusive OR W with f Syntax: XORWF Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) .XOR. (f) → dest Status Affected: N, Z Encoding: 0001 Description: f {,d {,a}} 10da ffff ffff Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank.
PIC18F87J10 FAMILY 25.2 Extended Instruction Set A summary of the instructions in the extended instruction set is provided in Table 25-3. Detailed descriptions are provided in Section 25.2.2 “Extended Instruction Set”. The opcode field descriptions in Table 25-1 (page 294) apply to both the standard and extended PIC18 instruction sets.
PIC18F87J10 FAMILY 25.2.2 EXTENDED INSTRUCTION SET ADDFSR Add Literal to FSR ADDULNK Syntax: ADDFSR f, k Syntax: ADDULNK k Operands: 0 ≤ k ≤ 63 f ∈ [ 0, 1, 2 ] Operands: 0 ≤ k ≤ 63 Operation: FSR(f) + k → FSR(f) Status Affected: None Encoding: 1110 Add Literal to FSR2 and Return FSR2 + k → FSR2, Operation: (TOS) → PC Status Affected: 1000 ffkk kkkk Description: The 6-bit literal ‘k’ is added to the contents of the FSR specified by ‘f’.
PIC18F87J10 FAMILY CALLW Subroutine Call using WREG MOVSF Move Indexed to f Syntax: CALLW Syntax: MOVSF [zs], fd Operands: None Operands: Operation: (PC + 2) → TOS, (W) → PCL, (PCLATH) → PCH, (PCLATU) → PCU 0 ≤ zs ≤ 127 0 ≤ fd ≤ 4095 Operation: ((FSR2) + zs) → fd Status Affected: None Status Affected: None Encoding: 0000 Description 0000 0001 0100 First, the return address (PC + 2) is pushed onto the return stack.
PIC18F87J10 FAMILY MOVSS Move Indexed to Indexed PUSHL Store Literal at FSR2, Decrement FSR2 Syntax: MOVSS [zs], [zd] Syntax: PUSHL k Operands: 0 ≤ zs ≤ 127 0 ≤ zd ≤ 127 Operands: 0 ≤ k ≤ 255 Operation: k → (FSR2), FSR2 – 1 → FSR2 Status Affected: None Operation: ((FSR2) + zs) → ((FSR2) + zd) Status Affected: None Encoding: 1st word (source) 2nd word (dest.
PIC18F87J10 FAMILY SUBFSR Subtract Literal from FSR SUBULNK Syntax: SUBFSR f, k Syntax: SUBULNK k Operands: 0 ≤ k ≤ 63 Operands: 0 ≤ k ≤ 63 f ∈ [ 0, 1, 2 ] Operation: FSR2 – k → FSR2, Operation: FSRf – k → FSRf Status Affected: None Encoding: 1110 (TOS) → PC Status Affected: 1001 ffkk kkkk Description: The 6-bit literal ‘k’ is subtracted from the contents of the FSR specified by ‘f’.
PIC18F87J10 FAMILY 25.2.3 Note: BYTE-ORIENTED AND BIT-ORIENTED INSTRUCTIONS IN INDEXED LITERAL OFFSET MODE Enabling the PIC18 instruction set extension may cause legacy applications to behave erratically or fail entirely. In addition to eight new commands in the extended set, enabling the extended instruction set also enables Indexed Literal Offset Addressing (Section 6.6.1 “Indexed Addressing with Literal Offset”).
PIC18F87J10 FAMILY ADD W to Indexed (Indexed Literal Offset mode) BSF Bit Set Indexed (Indexed Literal Offset mode) Syntax: ADDWF Syntax: BSF [k], b Operands: 0 ≤ k ≤ 95 d ∈ [0,1] Operands: 0 ≤ f ≤ 95 0≤b≤7 Operation: (W) + ((FSR2) + k) → dest Operation: 1 → ((FSR2) + k) Status Affected: N, OV, C, DC, Z Status Affected: None ADDWF Encoding: [k] {,d} 0010 Description: 01d0 kkkk kkkk The contents of W are added to the contents of the register indicated by FSR2, offset by the valu
PIC18F87J10 FAMILY 25.2.5 SPECIAL CONSIDERATIONS WITH MICROCHIP MPLAB® IDE TOOLS The latest versions of Microchip’s software tools have been designed to fully support the extended instruction set for the PIC18F87J10 family. This includes the MPLAB C18 C Compiler, MPASM assembly language and MPLAB Integrated Development Environment (IDE). When selecting a target device for software development, MPLAB IDE will automatically set default Configuration bits for that device.
PIC18F87J10 FAMILY 26.
PIC18F87J10 FAMILY 26.2 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging.
PIC18F87J10 FAMILY 26.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment.
PIC18F87J10 FAMILY 26.11 PICSTART Plus Development Programmer 26.13 Demonstration, Development and Evaluation Boards The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins.
PIC18F87J10 FAMILY 27.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any digital only I/O pin or MCLR with respect to VSS (except VDD) ....................................
PIC18F87J10 FAMILY FIGURE 27-1: PIC18F87J10 FAMILY VOLTAGE-FREQUENCY GRAPH, REGULATOR DISABLED (INDUSTRIAL) 3.00V Voltage (VDDCORE)(1) 2.75V 2.7V 2.50V PIC18F6XJ10/6XJ15/8XJ10/8XJ15 2.35V 2.25V 2.00V 4 MHz Frequency 40 MHz For VDDCORE values, 2V to 2.35V, FMAX = (102.85 MHz/V) * (VDDCORE – 2V) + 4 MHz Note 1: DS39663F-page 348 For devices without the voltage regulator, VDD and VDDCORE must be maintained so that VDDCORE ≤ VDD ≤ 3.6V. © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY FIGURE 27-2: PIC18F87J10 FAMILY VOLTAGE-FREQUENCY GRAPH, REGULATOR ENABLED (INDUSTRIAL) 4.0V 3.6V Voltage (VDD) 3.5V PIC18F6XJ10/6XJ15/8XJ10/8XJ15 3.0V 2.7V 2.5V 40 MHz 4 MHz Frequency • FMAX = 25 MHz in 8-bit External Memory mode. • FMAX = 40 MHz in all other modes for VDD > 2.35V. © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 27.1 DC Characteristics: Supply Voltage, PIC18F87J10 Family (Industrial) PIC18F87J10 Family (Industrial) Param No. Symbol Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Characteristic Supply Voltage D001 VDD D001B VDDCORE External Supply for Microcontroller Core D001C Min Typ Max Units Conditions VDDCORE 2.7 — — 3.6 3.6 V V ENVREG = 0 ENVREG = 1 2.0 — 2.
PIC18F87J10 FAMILY 27.2 DC Characteristics: PIC18F87J10 Family (Industrial) Param No.
PIC18F87J10 FAMILY 27.2 DC Characteristics: PIC18F87J10 Family (Industrial) Param No. Power-Down and Supply Current PIC18F87J10 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Device Typ Max Units Conditions Supply Current (IDD)(2,3) All devices All devices All devices All devices All devices All devices Note 1: 2: 3: 4: 5: 6: 1.8 3.27 mA -40°C 1.8 3.27 mA +25°C 1.9 3.27 mA +85°C 4.
PIC18F87J10 FAMILY 27.2 DC Characteristics: PIC18F87J10 Family (Industrial) Param No. Power-Down and Supply Current PIC18F87J10 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Device Typ Max Units Conditions 1.8 3.27 mA -40°C 1.8 3.27 mA +25°C 1.9 3.27 mA +85°C 4.0 5.57 mA -40°C 3.7 5.57 mA +25°C 3.5 5.57 mA +85°C 4.0 5.97 mA -40°C 3.8 5.97 mA +25°C 3.7 5.
PIC18F87J10 FAMILY 27.2 DC Characteristics: PIC18F87J10 Family (Industrial) Param No. Power-Down and Supply Current PIC18F87J10 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Device Typ Max Units Conditions 7.2 12.1 mA -40°C 6.8 12.1 mA +25°C 6.9 12.1 mA +85°C 7.6 13.1 mA -40°C 7.5 13.
PIC18F87J10 FAMILY 27.2 DC Characteristics: PIC18F87J10 Family (Industrial) Param No. Power-Down and Supply Current PIC18F87J10 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Device Typ Max Units Conditions 1.8 3.27 mA -40°C 1.8 3.27 mA +25°C 1.9 3.27 mA +85°C 4.0 5.57 mA -40°C 3.7 5.57 mA +25°C 3.5 5.57 mA +85°C 4.2 5.97 mA -40°C 4.0 5.97 mA +25°C 3.8 5.
PIC18F87J10 FAMILY 27.2 DC Characteristics: PIC18F87J10 Family (Industrial) Param No. Power-Down and Supply Current PIC18F87J10 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Device Typ Max Units Conditions 1.8 3.27 mA -10°C 1.8 3.27 mA +25°C 1.9 3.27 mA +70°C 4.0 5.57 mA -10°C 3.7 5.57 mA +25°C 3.5 5.57 mA +70°C 4.2 5.97 mA -10°C 4.0 5.97 mA +25°C 3.8 5.
PIC18F87J10 FAMILY 27.2 DC Characteristics: PIC18F87J10 Family (Industrial) Param No. D022 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Device Timer1 Oscillator (ΔIAD) Note 1: 2: 3: 4: 5: 6: Max Units Conditions -40°C A/D Converter D026 Typ Module Differential Currents (ΔIWDT, ΔIOSCB, ΔIAD) Watchdog Timer 1.9 4.5 μA (ΔIWDT) D025 (ΔIOSCB) Power-Down and Supply Current PIC18F87J10 Family (Industrial) (Continued) 1.9 1.3 2.
PIC18F87J10 FAMILY 27.3 DC Characteristics: PIC18F87J10 Family (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial DC CHARACTERISTICS Param Symbol No. VIL Characteristic Min Max Units Conditions VSS 0.15 VDD V VDD < 3.3V — 0.8 V 3.3V ≤ VDD ≤ 3.6V VSS 0.2 VDD V VSS 0.
PIC18F87J10 FAMILY 27.3 DC Characteristics: PIC18F87J10 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial DC CHARACTERISTICS Param Symbol No. D070 Characteristic Min Max Units 30 240 μA VDD = 3.3V, VPIN = VSS I/O Ports (PORTB, PORTC) — 0.4 V IOL = 8.5 mA, VDD 3.3V I/O Ports (PORTD, PORTE, PORTJ) — 0.4 V IOL = 3.4 mA, VDD 3.3V I/O Ports (PORTA, PORTF, PORTG, PORTH) — 0.4 V IOL = 3.
PIC18F87J10 FAMILY TABLE 27-1: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial DC CHARACTERISTICS Param No. Sym Characteristic Min Typ† Max Units Conditions Program Flash Memory D130 EP Cell Endurance 100 1K — E/W -40°C to +85°C D131 VPR VDD for Read VMIN — 3.6 V VMIN = Minimum operating voltage D132 VPEW Voltage for Self-Timed Erase or Write VDD 2.35 — 3.
PIC18F87J10 FAMILY TABLE 27-2: COMPARATOR SPECIFICATIONS Operating Conditions: 3.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated) Param No. Sym Characteristics Min Typ Max Units D300 VIOFF Input Offset Voltage — ±5.0 ±25 mV D301 VICM Input Common Mode Voltage 0 — VDD – 1.
PIC18F87J10 FAMILY 27.4 27.4.1 AC (Timing) Characteristics TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2.
PIC18F87J10 FAMILY 27.4.2 TIMING CONDITIONS The temperature and voltages specified in Table 27-5 apply to all timing specifications unless otherwise noted. Figure 27-3 specifies the load conditions for the timing specifications. TABLE 27-5: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC AC CHARACTERISTICS FIGURE 27-3: Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Operating voltage VDD range as described in DC spec Section 27.
PIC18F87J10 FAMILY 27.4.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 27-4: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL) Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 4 3 4 2 CLKO TABLE 27-6: Param. No.
PIC18F87J10 FAMILY TABLE 27-7: Param No. F10 PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.7V TO 3.6V) Sym Characteristic Min Typ† Max Units 4 16 — — 10 40 MHz MHz F11 FOSC Oscillator Frequency Range FSYS On-Chip VCO System Frequency F12 trc PLL Start-up Time (Lock Time) — — 2 ms ΔCLK CLKO Stability (Jitter) -2 — +2 % F13 Conditions † Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance only and are not tested. TABLE 27-8: Param No.
PIC18F87J10 FAMILY FIGURE 27-5: CLKO AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKO 13 14 19 12 18 16 I/O pin (Input) 15 17 I/O pin (Output) New Value Old Value 20, 21 Note: Refer to Figure 27-3 for load conditions. TABLE 27-9: Param No.
PIC18F87J10 FAMILY FIGURE 27-6: PROGRAM MEMORY FETCH TIMING DIAGRAM (8-BIT) Q1 Q2 Q3 Q4 Q1 Q2 OSC1 A<19:8> Address Address 167 166 150 161 151 AD<7:0> Data Data Address Address 162 153 162A 154 155 BA0 163 170 170A ALE 168 CE OE TABLE 27-7: Param No PROGRAM MEMORY FETCH TIMING REQUIREMENTS (8-BIT) Symbol Characteristics Min Typ Max Units 150 TadV2aIL Address Out Valid to ALE ↓ (address setup time) 0.
PIC18F87J10 FAMILY FIGURE 27-8: PROGRAM MEMORY READ TIMING DIAGRAM Q1 Q2 Q3 Q4 Q1 Q2 OSC1 A<19:16> BA0 AD<15:0> Address Address Address Data from External 150 151 Address 163 160 162 161 155 166 167 ALE 168 164 171 169 CE 171A OE 165 Operating Conditions: 2.0V < VCC < 3.6V, -40°C < TA < +125°C unless otherwise stated. TABLE 27-10: CLKO AND I/O TIMING REQUIREMENTS Param. No Symbol Characteristics Min Typ Max Units 0.
PIC18F87J10 FAMILY FIGURE 27-9: PROGRAM MEMORY WRITE TIMING DIAGRAM Q1 Q2 Q3 Q4 Q1 Q2 OSC1 A<19:16> BA0 Address Address 166 AD<15:0> Data Address Address 153 150 156 151 ALE 171 CE 171A 154 WRH or WRL 157A 157 UB or LB Operating Conditions: 2.0V < VCC < 3.6V, -40°C < TA < +125°C unless otherwise stated. TABLE 27-11: PROGRAM MEMORY WRITE TIMING REQUIREMENTS Param. No Symbol Characteristics Min Typ Max Units 150 TadV2alL Address Out Valid to ALE ↓ (address setup time) 0.
PIC18F87J10 FAMILY FIGURE 27-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 Oscillator Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O pins Note: Refer to Figure 27-3 for load conditions. TABLE 27-12: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param. Symbol No.
PIC18F87J10 FAMILY FIGURE 27-11: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 41 40 42 T1OSO/T13CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 27-3 for load conditions. TABLE 27-13: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param No.
PIC18F87J10 FAMILY FIGURE 27-12: CAPTURE/COMPARE/PWM TIMINGS (INCLUDING ECCP MODULES) CCPx (Capture Mode) 50 51 52 CCPx (Compare or PWM Mode) 54 53 Note: Refer to Figure 27-3 for load conditions. TABLE 27-14: CAPTURE/COMPARE/PWM REQUIREMENTS (INCLUDING ECCP MODULES) Param Symbol No. 50 51 TCCL TCCH Characteristic Min Max Units CCPx Input Low No prescaler Time With prescaler 0.5 TCY + 20 — ns 10 — ns CCPx Input High Time 0.
PIC18F87J10 FAMILY FIGURE 27-13: EXAMPLE SPI MASTER MODE TIMING (CKE = 0) SSx 70 SCKx (CKP = 0) 71 72 78 79 79 78 SCKx (CKP = 1) 80 bit 6 - - - - - - 1 MSb SDOx LSb 75, 76 SDIx MSb In bit 6 - - - - 1 LSb In 74 73 Note: Refer to Figure 27-3 for load conditions. TABLE 27-16: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0) Param No.
PIC18F87J10 FAMILY FIGURE 27-14: EXAMPLE SPI MASTER MODE TIMING (CKE = 1) SSx 81 SCKx (CKP = 0) 71 72 79 73 SCKx (CKP = 1) 80 78 MSb SDOx bit 6 - - - - - - 1 LSb bit 6 - - - - 1 LSb In 75, 76 SDIx MSb In 74 Note: Refer to Figure 27-3 for load conditions. TABLE 27-17: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1) Param. No.
PIC18F87J10 FAMILY FIGURE 27-15: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0) SSx 70 SCKx (CKP = 0) 83 71 72 78 79 79 78 SCKx (CKP = 1) 80 MSb SDOx bit 6 - - - - - - 1 LSb 75, 76 MSb In SDIx SDI 77 bit 6 - - - - 1 LSb In 74 73 Note: Refer to Figure 27-3 for load conditions. TABLE 27-18: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0) Param No.
PIC18F87J10 FAMILY FIGURE 27-16: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1) 82 SSx SCKx (CKP = 0) 70 83 71 72 SCKx (CKP = 1) 80 MSb SDOx bit 6 - - - - - - 1 LSb 75, 76 SDIx SDI Note: MSb In 77 bit 6 - - - - 1 LSb In 74 Refer to Figure 27-3 for load conditions. TABLE 27-19: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1) Param No.
PIC18F87J10 FAMILY FIGURE 27-17: I2C™ BUS START/STOP BITS TIMING SCLx 91 93 90 92 SDAx Stop Condition Start Condition Note: Refer to Figure 27-3 for load conditions. TABLE 27-20: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol No.
PIC18F87J10 FAMILY TABLE 27-21: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE) Param. No. 100 Symbol THIGH 101 TLOW 102 TR Characteristic Clock High Time Clock Low Time Min Max Units 100 kHz mode 4.0 — μs 400 kHz mode 0.6 — μs MSSP Module 1.5 TCY — 100 kHz mode 4.7 — μs μs 400 kHz mode 1.3 — MSSP Module 1.5 TCY — — 1000 ns 20 + 0.
PIC18F87J10 FAMILY FIGURE 27-19: MASTER SSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS SCLx 93 91 90 92 SDAx Stop Condition Start Condition Note: Refer to Figure 27-3 for load conditions. TABLE 27-22: MASTER SSP I2C™ BUS START/STOP BITS REQUIREMENTS Param. Symbol No.
PIC18F87J10 FAMILY TABLE 27-23: MASTER SSP I2C™ BUS DATA REQUIREMENTS Param. Symbol No. 100 101 THIGH TLOW Characteristic Min Max Units Clock High Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms (1) 2(TOSC)(BRG + 1) — ms — 1000 ns 20 + 0.
PIC18F87J10 FAMILY FIGURE 27-21: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING TXx/CKx pin 121 121 RXx/DTx pin 120 Note: 122 Refer to Figure 27-3 for load conditions. TABLE 27-24: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param No.
PIC18F87J10 FAMILY TABLE 27-26: A/D CONVERTER CHARACTERISTICS: PIC18F87J10 FAMILY (INDUSTRIAL) Param Symbol No. Characteristic Min Typ Max Units — — 10 bit Conditions A01 NR Resolution A03 EIL Integral Linearity Error — — <±1 LSb ΔVREF ≥ 3.0V A04 EDL Differential Linearity Error — — <±1 LSb ΔVREF ≥ 3.0V A06 EOFF Offset Error — — <±3 LSb ΔVREF ≥ 3.0V A07 EGN Gain Error — — <±3 LSb ΔVREF ≥ 3.
PIC18F87J10 FAMILY TABLE 27-27: A/D CONVERSION REQUIREMENTS Param Symbol No. Characteristic Min Max Units 130 TAD A/D Clock Period 0.7 25.0(1) μs 131 TCNV Conversion Time (not including acquisition time) (Note 2) 11 12 TAD 132 TACQ Acquisition Time (Note 3) 1.4 — μs 135 TSWC Switching Time from Convert → Sample — (Note 4) 136 TDIS Discharge Time 0.2 — Note 1: 2: 3: 4: Conditions TOSC based, VREF ≥ 3.
PIC18F87J10 FAMILY NOTES: DS39663F-page 384 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY 28.0 PACKAGING INFORMATION 28.1 Package Marking Information 64-Lead TQFP XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 80-Lead TQFP XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Legend: XX...
PIC18F87J10 FAMILY 28.2 Package Details The following sections give the technical details of the packages.
PIC18F87J10 FAMILY ' ( !" #$ % & 3 & ' !& " & 4 && 255*** ' '5 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY ) ' ( # # !" #$ % & 3 & ' !& " & 4 && 255*** ' '5 # * !( 4 ! ! & 4 % & & # & D D1 E e E1 N b NOTE 1 12 3 NOTE 2 c φ β L α A A2 A1 L1 6 &! ' ! 7 ' &! 8"') % 7 7 # & 9 < & #! 8 89 : @ / 1 + = = / / / = / 3 & 7 & 7 / ; / 3 & & 7 # # 4 4
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PIC18F87J10 FAMILY NOTES: DS39663F-page 390 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY APPENDIX A: MIGRATION BETWEEN HIGH-END DEVICE FAMILIES Devices in the PIC18F87J10 and PIC18F8722 families are very similar in their functions and feature sets. However, there are some potentially important differences which should be considered when migrating an application across device families to achieve a new design goal. These are summarized in Table A-1. The areas of difference which could be a major impact on migration are discussed in greater detail later in this section.
PIC18F87J10 FAMILY A.1 Power Requirement Differences The most significant difference between the PIC18F87J10 and PIC18F8722 device families is the power requirements. PIC18F87J10 devices are designed on a smaller process; this results in lower maximum voltage and higher leakage current. The operating voltage range for PIC18F87J10 devices is 2.0V to 3.6V. In addition, these devices have split power requirements: one for the core logic and one for the I/O.
PIC18F87J10 FAMILY APPENDIX B: REVISION HISTORY Revision A (December 2004) Original data sheet for PIC18F87J10 family devices. Revision B (July 2005) Packaging diagrams have been updated. Document updated from Advanced to Preliminary. Updated all TBDs in Section 27.0 “Electrical Characteristics”. Edits to text throughout document. Revision C (December 2005) Packaging diagrams have been updated. Minor edits to text throughout document.
PIC18F87J10 FAMILY NOTES: DS39663F-page 394 © 2009 Microchip Technology Inc.
PIC18F87J10 FAMILY INDEX A A/D ................................................................................... 261 A/D Converter Interrupt, Configuring ....................... 265 Acquisition Requirements ........................................ 266 ADCAL Bit ................................................................ 269 ADCON0 Register .................................................... 261 ADCON1 Register .................................................... 261 ADCON2 Register .................
PIC18F87J10 FAMILY BSF .................................................................................. 305 BTFSC ............................................................................. 306 BTFSS .............................................................................. 306 BTG .................................................................................. 307 BZ ..................................................................................... 308 C C Compilers MPLAB C18 ................
PIC18F87J10 FAMILY Memory Maps PIC18FX5J10/X5J15/X6J10 Devices ................ 69 PIC18FX6J15/X7J10 Devices ........................... 70 Special Function Registers ................................ 72 Special Function Registers ........................................ 72 DAW ................................................................................. 312 DC Characteristics ........................................................... 358 Power-Down and Supply Current ............................
PIC18F87J10 FAMILY Erase Sequence ........................................................ 90 Erasing ....................................................................... 90 Operation During Code-Protect ................................. 93 Reading ...................................................................... 89 Table Pointer Boundaries Based on Operation ........................ 88 Table Pointer Boundaries .......................................... 88 Table Reads and Table Writes ..............
PIC18F87J10 FAMILY POP ......................................................................... 322 PUSH ....................................................................... 322 RCALL ..................................................................... 323 RESET ..................................................................... 323 RETFIE .................................................................... 324 RETLW .................................................................... 324 RETURN ....
PIC18F87J10 FAMILY Pin Functions AVDD .......................................................................... 16 AVDD .......................................................................... 25 AVSS .......................................................................... 16 AVSS .......................................................................... 25 ENVREG .............................................................. 16, 25 MCLR .................................................................
PIC18F87J10 FAMILY PORTD Associated Registers ............................................... 136 LATD Register ......................................................... 134 PORTD Register ...................................................... 134 TRISD Register ........................................................ 134 PORTE Analog Port Pins ...................................................... 148 Associated Registers ............................................... 139 LATE Register ...................
PIC18F87J10 FAMILY RCON Register Bit Status During Initialization .................................... 52 Reader Response ............................................................ 406 Register File ....................................................................... 71 Register File Summary ................................................. 73–76 Registers ADCON0 (A/D Control 0) ......................................... 261 ADCON1 (A/D Control 1) .........................................
PIC18F87J10 FAMILY SSPOV Status Flag ......................................................... 229 SSPxSTAT Register R/W Bit ............................................................. 209, 211 SSx .................................................................................. 193 Stack Full/Underflow Resets .............................................. 65 SUBFSR .......................................................................... 339 SUBFWB ......................................................
PIC18F87J10 FAMILY I2C Slave Mode (10-Bit Reception, SEN = 0, ADMSK = 01001) ............................................. 215 I2C Slave Mode (10-Bit Reception, SEN = 0) .......... 216 I2C Slave Mode (10-Bit Reception, SEN = 1) .......... 221 I2C Slave Mode (10-Bit Transmission) ..................... 217 I2C Slave Mode (7-Bit Reception, SEN = 0, ADMSK = 01011) ............................................. 213 I2C Slave Mode (7-Bit Reception, SEN = 0) ............
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PIC18F87J10 FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO.
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