Datasheet

 2009-2011 Microchip Technology Inc. DS39957D-page 541
PIC18F87K90 FAMILY
FIGURE 31-19: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 31-22: EUSART/AUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 31-20: EUSART/AUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 31-23: EUSART/AUSART SYNCHRONOUS RECEIVE REQUIREMENTS
TABLE 31-24: ULTRA LOW-POWER WAKE-UP SPECIFICATIONS
Param
No.
Symbol Characteristic Min Max Units Conditions
120 TCKH2DTV SYNC XMIT (MASTER and SLAVE)
Clock High to Data Out Valid — 40 ns
121 T
CKRF Clock Out Rise Time and Fall Time (Master mode) — 20 ns
122 T
DTRF Data Out Rise Time and Fall Time — 20 ns
Param.
No.
Symbol Characteristic Min Max Units Conditions
125 TDTV2CKL SYNC RCV (MASTER and SLAVE)
Data Hold before CKx  (DTx hold time) 10 — ns
126 T
CKL2DTL Data Hold after CKx  (DTx hold time) 15 — ns
Standard Operating Conditions: 3.0V < VDD < 3.6V
Operating temperature -40°C  TA  +85°C (unless otherwise stated)
Param.
No.
Symbol Characteristic Min Typ Max Units Comments
Dxxx IULP Ultra Low-Power Wake-up Sink Current — 60 — nA Net of I/O leakage and current
sink at 1.6V on pin,
V
DD = 3.3V
121
121
120
122
TXx/CKx
RXx/DTx
Pin
Pin
Note: Refer to Figure 31-3 for load conditions.
125
126
TXx/CKx
RXx/DTx
Pin
Pin
Note: Refer to Figure 31-3 for load conditions.