Datasheet

PIC18F87K90 FAMILY
DS39957D-page 248  2009-2011 Microchip Technology Inc.
A PWM output (Figure 18-4) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
FIGURE 18-4: PWM OUTPUT
18.4.1 PWM PERIOD
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula:
EQUATION 18-1:
PWM frequency is defined as 1/[PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The CCP4 pin is set
(An exception: If PWM duty cycle = 0%, the CCP4
pin will not be set)
• The PWM duty cycle is latched from CCPR4L into
CCPR4H
18.4.2 PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR4L register (using CCP4 as an example) and to
the CCP4CON<5:4> bits. Up to 10-bit resolution is avail-
able. The CCPR4L contains the eight MSbs and the
CCP4CON<5:4> bits contain the two LSbs. This 10-bit
value is represented by CCPR4L:CCP4CON<5:4>. The
following equation is used to calculate the PWM duty
cycle in time:
EQUATION 18-2:
CCPR4L and CCP4CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR4H until after a match between PR2 and TMR2
occurs (that is, the period is complete). In PWM mode,
CCPR4H is a read-only register.
The CCPR4H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM
operation.
When the CCPR4H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or two bits
of the TMR2 prescaler, the CCP4 pin is cleared.
The maximum PWM resolution (bits) for a given PWM
frequency is given by Equation 18-3:
EQUATION 18-3:
TABLE 18-6: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
Note: The Timer2 postscalers (see
Section 14.0 “Timer2 Module”) are not
used in the determination of the PWM
frequency. The postscaler could be used
to have a servo update rate at a different
frequency than the PWM output.
Period
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = PR2
PWM Period = [(PR2) + 1] • 4 • TOSC •
(TMR2 Prescale Value)
Note: If the PWM duty cycle value is longer than
the PWM period, the CCP4 pin will not be
cleared.
PWM Duty Cycle = (CCPR4L:CCP4CON<5:4>) •
T
OSC • (TMR2 Prescale Value)
FOSC
FPWM
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PWM Resolution (max)
PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz
Timer Prescaler (1, 4, 16)1641111
PR2 Value FFh FFh FFh 3Fh 1Fh 17h
Maximum Resolution (bits) 14 12 10 8 7 6.58