Datasheet
PIC18F87K22 FAMILY
DS39960D-page 98 2009-2011 Microchip Technology Inc.
F3Fh TMR7H
(3)
F32h TMR12
(3)
F25h ANCON0 F18h PMD1
F3Eh TMR7L
(3)
F31h PR12
(3)
F24h ANCON1 F17h PMD2
F3Dh T7CON
(3)
F30h T12CON
(3)
F23h ANCON2 F16h PMD3
F3Ch T7GCON
(3)
F2Fh CM2CON F22h RCSTA2
F3Bh TMR6 F2Eh CM3CON F21h TXSTA2
F3Ah PR6 F2Dh CCPTMRS0 F20h BAUDCON2
F39H T6CON F2Ch CCPTMRS1 F1Fh SPBRGH2
F38h TMR8 F2Bh CCPTMRS2 F1Eh SPBRG2
F37h PR8 F2Ah REFOCON F1Dh RCREG2
F36h T8CON F29H ODCON1 F1Ch TXREG2
F35h TMR10
(3)
F28h ODCON2 F1Bh PSTR2CON
F34h PR10
(3)
F27h ODCON3 F1Ah PSTR3CON
F33h T10CON
(3)
F26h MEMCON
(3)
F19h PMD0
TABLE 6-2: PIC18F87K22 FAMILY REGISTER FILE SUMMARY
Address File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
FFFh TOSU
— — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000
FFEh TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000
FFDh TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000
FFCh STKPTR STKFUL STKUNF
— Return Stack Pointer uu-0 0000
FFBh PCLATU
— — — Holding Register for PC<20:16> ---0 0000
FFAh PCLATH Holding Register for PC<15:8> 0000 0000
FF9h PCL PC Low Byte (PC<7:0>) 0000 0000
FF8h TBLPTRU
— — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000
FF7h TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000
FF6h TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000
FF5h TABLAT Program Memory Table Latch 0000 0000
FF4h PRODH Product Register High Byte xxxx xxxx
FF3h PRODL Product Register Low Byte xxxx xxxx
FF2h INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x
FF1h INTCON2 RBPU
INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 1111 1111
FF0h INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF 1100 0000
FEFh INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) ---- ----
FEEh POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) ---- ----
FEDh POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) ---- ----
FECh PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) ---- ----
FEBh PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) – value of
FSR0 offset by W
---- ----
FEAh FSR0H
— — — — Indirect Data Memory Address Pointer 0 High ---- 0000
FE9h FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx
FE8h WREG Working Register xxxx xxxx
FE7h INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) ---- ----
Note 1: This bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, the bit is unimplemented.
2: Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’.
3: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22).
TABLE 6-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F87K22 FAMILY (CONTINUED)
Addr.
Name
Addr.
Name
Addr.
Name
Addr.
Name
Addr.
Name
Addr.
Name
(4)
Note 1: This is not a physical register.
2: Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’.
3: This register is not available on devices with a program memory of 32 Kbytes (PIC18FX5K22).
4: Addresses, F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM. To access these registers,
users must always load the proper BSR value.