Datasheet

 2009-2011 Microchip Technology Inc. DS39960D-page 65

PIC18F87K22 FAMILY

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CCP10MD

(1)

CCP9MD

(1)

CCP8MD CCP7MD CCP6MD CCP5MD CCP4MD TMR12MD

(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 CCP10MD: PMD CCP10 Enable/Disable bit

(1)

1 = Peripheral Module Disable (PMD) is enabled for CCP10, disabling all of its clock sources

0 = PMD is disabled for CCP10

bit 6 CCP9MD: PMD CCP9 Enable/Disable bit

(1)

1 = Peripheral Module Disable (PMD) is enabled for CCP9, disabling all of its clock sources

0 = PMD is disabled for CCP9

bit 5 CCP8MD: PMD CCP8 Enable/Disable bit

1 = Peripheral Module Disable (PMD) is enabled for CCP8, disabling all of its clock sources

0 = PMD is disabled for CCP8

bit 4 CCP7MD: PMD CCP7 Enable/Disable bit

1 = Peripheral Module Disable (PMD) is enabled for CCP7, disabling all of its clock sources

0 = PMD is disabled for CCP7

bit 3 CCP6MD: PMD CCP6 Enable/Disable bit

1 = Peripheral Module Disable (PMD) is enabled for CCP6, disabling all of its clock sources

0 = PMD is disabled for CCP6

bit 2 CCP5MD: PMD CCP5 Enable/Disable bit

1 = Peripheral Module Disable (PMD) is enabled for CCP5, disabling all of its clock sources

0 = PMD is disabled for CCP5

bit 1 CCP4MD: PMD CCP4 Enable/Disable bit

1 = Peripheral Module Disable (PMD) is enabled for CCP4, disabling all of its clock sources

0 = PMD is disabled for CCP4

bit 0 TMR12MD: TMR12MD Disable bit

(1)

1 = PMD is enabled and all TMR12MD clock sources are disabled

0 = PMD is disabled and TMR12MD is enabled

Note 1: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22).