Datasheet

 2009-2011 Microchip Technology Inc. DS39960D-page 545
PIC18F87K22 FAMILY
Timer4/6/8/10/12............................................................... 223
Associated Registers ................................................ 225
Interrupt..................................................................... 224
Operation .................................................................. 223
Output ....................................................................... 224
Postscaler.
See Postscaler, Timer4/6/8/10/12.
Prescaler.
See Prescaler, Timer4/6/8/10/12.
PRx Register............................................................. 223
TMRx Register .......................................................... 223
Timing Diagrams
A/D Conversion......................................................... 524
Asynchronous Reception .......................................... 341
Asynchronous Transmission..................................... 338
Asynchronous Transmission (Back-to-Back) ............ 338
Automatic Baud Rate Calculation ............................. 336
Auto-Wake-up Bit (WUE) During Normal
Operation .......................................................... 343
Auto-Wake-up Bit (WUE) During Sleep .................... 343
Baud Rate Generator with Clock Arbitration ............. 314
BRG Overflow Sequence.......................................... 336
BRG Reset Due to SDAx Arbitration During
Start Condition .................................................. 323
Brown-out Reset (BOR)............................................ 509
Bus Collision During Repeated Start Condition
(Case 1) ............................................................ 324
Bus Collision During Repeated Start Condition
(Case 2) ............................................................ 324
Bus Collision During Start Condition (SCLx = 0) ...... 323
Bus Collision During Start Condition (SDAx Only).... 322
Bus Collision During Stop Condition (Case 1) .......... 325
Bus Collision During Stop Condition (Case 2) .......... 325
Bus Collision for Transmit and Acknowledge............ 321
Capture/Compare/PWM............................................ 513
CLKO and I/O ........................................................... 505
Clock Synchronization .............................................. 307
Clock/Instruction Cycle ............................................... 92
EUSART Synchronous Transmission
(Master/Slave) .................................................. 522
EUSART/AUSART Synchronous Receive
(Master/Slave) .................................................. 522
Example SPI Master Mode (CKE = 0) ...................... 514
Example SPI Master Mode (CKE = 1) ...................... 515
Example SPI Slave Mode (CKE = 0) ........................ 516
Example SPI Slave Mode (CKE = 1) ........................ 517
External Clock........................................................... 503
External Memory Bus for SLEEP (Extended
Microcontroller Mode) ............................... 128, 130
External Memory Bus for TBLRD (Extended
Microcontroller Mode) ............................... 128, 130
Fail-Safe Clock Monitor (FSCM)............................... 425
First Start Bit Timing ................................................. 315
Full-Bridge PWM Output ........................................... 270
Half-Bridge PWM Output .................................. 268, 275
High-Voltage Detect Operation (VDIRMAG = 1)....... 383
HLVD Characteristics................................................ 511
I
2
C Acknowledge Sequence ..................................... 320
I
2
C Bus Data............................................................. 519
I
2
C Bus Start/Stop Bits.............................................. 518
I
2
C Master Mode (7 or 10-Bit Transmission) ............ 318
I
2
C Master Mode (7-Bit Reception)........................... 319
I
2
C Slave Mode (10-Bit Reception, SEN = 0,
ADMSK = 01001).............................................. 303
I
2
C Slave Mode (10-Bit Reception, SEN = 0) ........... 304
I
2
C Slave Mode (10-Bit Reception, SEN = 1) ........... 309
I
2
C Slave Mode (10-Bit Transmission)...................... 305
I
2
C Slave Mode (7-bit Reception, SEN = 0,
ADMSK = 01011) ............................................. 301
I
2
C Slave Mode (7-Bit Reception, SEN = 0)............. 300
I
2
C Slave Mode (7-Bit Reception, SEN = 1)............. 308
I
2
C Slave Mode (7-Bit Transmission) ....................... 302
I
2
C Slave Mode General Call Address Sequence
(7 or 10-Bit Addressing Mode).......................... 310
I
2
C Stop Condition Receive or Transmit Mode......... 320
Low-Voltage Detect Operation (VDIRMAG = 0) ....... 382
MSSP I
2
C Bus Data ................................................. 520
MSSP I
2
C Bus Start/Stop Bits.................................. 520
Parallel Slave Port (PSP) Read................................ 191
Parallel Slave Port (PSP) Write ................................ 190
Program Memory Fetch (8-bit) ................................. 506
Program Memory Read ............................................ 507
Program Memory Write ............................................ 508
PWM Auto-Shutdown with Auto-Restart Enabled
(PxRSEN = 1)................................................... 274
PWM Auto-Shutdown with Firmware Restart
(PxRSEN = 0)................................................... 274
PWM Direction Change ............................................ 271
PWM Direction Change at Near 100%
Duty Cycle ........................................................ 272
PWM Output ............................................................. 255
PWM Output (Active-High) ....................................... 266
PWM Output (Active-Low) ........................................ 267
Repeated Start Condition ......................................... 316
Reset, Watchdog Timer (WDT), Oscillator Start-up
Timer (OST) and Power-up Timer (PWRT) ...... 509
Send Break Character Sequence............................. 344
Slave Synchronization .............................................. 287
Slow Rise Time (MCLR
Tied to VDD,
V
DD Rise > TPWRT)............................................. 77
SPI Mode (Master Mode) ......................................... 286
SPI Mode (Slave Mode, CKE = 0)............................ 288
SPI Mode (Slave Mode, CKE = 1)............................ 288
Steering Event at Beginning of Instruction
(STRSYNC = 1)................................................ 278
Steering Event at End of Instruction
(STRSYNC = 0)................................................ 278
Synchronous Reception (Master Mode, SREN) ....... 347
Synchronous Transmission ...................................... 345
Synchronous Transmission (Through TXEN) ........... 346
Time-out Sequence on Power-up (MCLR
Not Tied to V
DD), Case 1.................................... 77
Time-out Sequence on Power-up (MCLR
Not Tied to V
DD), Case 2.................................... 77
Time-out Sequence on Power-up (MCLR
Tied to V
DD, VDD Rise TPWRT) ........................... 76
Timer Pulse Generation............................................ 242
Timer0 and Timer1 External Clock ........................... 512
Timer1 Gate Count Enable Mode............................. 204
Timer1 Gate Single Pulse Mode............................... 206
Timer1 Gate Single Pulse/Toggle
Combined Mode ............................................... 207
Timer1 Gate Toggle Mode........................................ 205
Timer3/5/7 Gate Count Enable Mode....................... 217
Timer3/5/7 Gate Single Pulse Mode......................... 219
Timer3/5/7 Gate Single Pulse/Toggle
Combined Mode ............................................... 220
Timer3/5/7 Gate Toggle Mode.................................. 218
Transition for Entry to Idle Mode ................................ 63
Transition for Entry to SEC_RUN Mode ..................... 59
Transition for Entry to Sleep Mode ............................. 62