Datasheet

PIC18F87K22 FAMILY
DS39960D-page 538  2009-2011 Microchip Technology Inc.
Synchronous Master Mode ....................................... 345
Associated Registers, Receive ......................... 348
Associated Registers, Transmit ........................346
Reception.......................................................... 347
Reception Sequence......................................... 347
Transmission..................................................... 345
Transmission Sequence ................................... 345
Synchronous Slave Mode ......................................... 349
Associated Registers, Receive ......................... 350
Associated Registers, Transmit ........................349
Reception.......................................................... 350
Reception Sequence......................................... 350
Transmission..................................................... 349
Transmission Sequence ................................... 349
Extended Instruction Set
ADDFSR ...................................................................474
ADDULNK................................................................. 474
CALLW......................................................................475
MOVSF ..................................................................... 475
MOVSS ..................................................................... 476
PUSHL ...................................................................... 476
SUBFSR ................................................................... 477
SUBULNK ................................................................. 477
External Memory Bus (EMB)............................................. 121
16-Bit Byte Write Mode ............................................. 125
16-Bit Data Width Modes .......................................... 124
16-Bit Mode Timing................................................... 128
16-Bit Word Write Mode............................................ 126
8-Bit Data Width Mode..............................................129
8-Bit Mode Timing ..................................................... 130
Address and Data Lines for Different Address
and Data Widths (table) .................................... 123
Address and Data Width ........................................... 123
Address Shifting........................................................ 123
Associated Registers ................................................ 131
Control ......................................................................122
I/O Port Functions ..................................................... 121
Operation in Power-Managed Modes ....................... 131
Program Memory Modes ..........................................124
Extended Microcontroller .................................. 124
Microcontroller .................................................. 124
Wait States................................................................ 124
Weak Pull-ups on Port Pins ...................................... 124
External Memory Bus EMB)
16-Bit Byte Select Mode ........................................... 127
External Oscillator Modes
Clock Input (EC Modes).............................................. 51
HS ............................................................................... 50
F
Fail-Safe Clock Monitor............................................. 403, 424
Exiting Operation ...................................................... 424
Interrupts in Power-Managed Modes ........................ 425
POR or Wake from Sleep .........................................425
WDT During Oscillator Failure ..................................424
Fast Register Stack............................................................. 91
Firmware Instructions........................................................431
Flash Program Memory..................................................... 111
Associated Registers ................................................ 120
Control Registers ...................................................... 112
EECON1 and EECON2 .................................... 112
TABLAT (Table Latch) Register........................ 114
TBLPTR (Table Pointer) Register .....................114
TBLPTR (Table Pointer) Register,
Boundaries................................................ 114
Erase Sequence ....................................................... 116
Erasing ..................................................................... 116
Operation During Code-Protect ................................ 120
Reading .................................................................... 115
Table Pointer
Boundaries Based on Operation ...................... 114
Table Reads and Table Writes ................................. 111
Write Sequence ........................................................ 118
Writing ...................................................................... 117
Protection Against Spurious Writes .................. 120
Unexpected Termination .................................. 120
Write Verify ....................................................... 120
FSCM.
See Fail-Safe Clock Monitor.
G
GOTO ............................................................................... 452
H
Hardware Multiplier........................................................... 139
8 x 8 Multiplication Algorithms .................................. 139
Operation.................................................................. 139
Performance Comparison (table).............................. 139
High/Low-Voltage Detect .................................................. 379
Applications .............................................................. 383
Associated Registers................................................ 384
Current Consumption................................................ 381
Effects of a Reset ..................................................... 384
Operation.................................................................. 380
During Sleep..................................................... 384
Setup ........................................................................ 381
Start-up Time............................................................ 381
Typical Application.................................................... 383
HLVD.
See High/Low-Voltage Detect.
I
I/O Ports............................................................................ 165
Open-Drain Outputs.................................................. 167
Output Pin Drive ....................................................... 165
Pin Capabilities......................................................... 165
Pull-up Configuration ................................................ 165
I
2
C Mode (MSSP)
Acknowledge Sequence Timing ............................... 320
Associated Registers................................................ 326
Baud Rate Generator ............................................... 313
Bus Collision
During a Repeated Start Condition................... 324
During a Stop Condition ................................... 325
Clock Arbitration ....................................................... 314
Clock Stretching........................................................ 306
10-Bit Slave Receive Mode (SEN = 1) ............. 306
10-Bit Slave Transmit Mode ............................. 306
7-Bit Slave Receive Mode (SEN = 1) ............... 306
7-Bit Slave Transmit Mode ............................... 306
Clock Synchronization and the CKP bit.................... 307
Effects of a Reset ..................................................... 321
General Call Address Support .................................. 310
I
2
C Clock Rate w/BRG.............................................. 313
Master Mode............................................................. 311
Operation.......................................................... 312
Reception ......................................................... 317
Repeated Start Condition Timing ..................... 316
Start Condition Timing ...................................... 315
Transmission .................................................... 317
Transmit Sequence .......................................... 312
Multi-Master Communication, Bus Collision
and Arbitration .................................................. 321
Multi-Master Mode.................................................... 321