Datasheet

PIC18F87K22 FAMILY
DS39960D-page 522  2011 Microchip Technology Inc.
FIGURE 31-22: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 31-25: EUSART/AUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 31-23: EUSART/AUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 31-26: EUSART/AUSART SYNCHRONOUS RECEIVE REQUIREMENTS
Param
No.
Symbol Characteristic Min Max Units Conditions
120 TCKH2DTV SYNC XMIT (MASTER and SLAVE)
Clock High to Data Out Valid — 40 ns
121 T
CKRF Clock Out Rise Time and Fall Time (Master mode) — 20 ns
122 T
DTRF Data Out Rise Time and Fall Time — 20 ns
Param.
No.
Symbol Characteristic Min Max Units Conditions
125 TDTV2CKL SYNC RCV (MASTER and SLAVE)
Data Hold before CKx  (DTx hold time) 10 — ns
126 T
CKL2DTL Data Hold after CKx  (DTx hold time) 15 — ns
121
121
120
122
TXx/CKx
RXx/DTx
Pin
Pin
Note: Refer to Figure 31-3 for load conditions.
125
126
TXx/CKx
RXx/DTx
Pin
Pin
Note: Refer to Figure 31-3 for load conditions.