Datasheet

 2011 Microchip Technology Inc. DS39960D-page 517
PIC18F87K22 FAMILY
FIGURE 31-17: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
TABLE 31-20: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param
No.
Symbol Characteristic Min Max Units Conditions
70 TSSL2SCH,
T
SSL2SCL
SSx
 to SCKx  or SCKx  Input 3 TCY —ns
70A T
SSL2WB SSx to Write to SSPBUF 3 TCY —ns
71 T
SCH SCKx Input High Time
(Slave mode)
Continuous 1.25 TCY + 30 — ns
71A Single Byte 40 — ns
(Note 1)
72 TSCL SCKx Input Low Time
(Slave mode)
Continuous 1.25 TCY + 30 — ns
72A Single Byte 40 — ns
(Note 1)
73A TB2B Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2)
74 TSCH2DIL,
T
SCL2DIL
Hold Time of SDIx Data Input to SCKx Edge 40 — ns
75 T
DOR SDOx Data Output Rise Time — 25 ns
76 T
DOF SDOx Data Output Fall Time — 25 ns
77 T
SSH2DOZ SSx  to SDOx Output High-Impedance 10 50 ns
78 T
SCR SCKx Output Rise Time (Master mode) — 25 ns
79 T
SCF SCKx Output Fall Time (Master mode) — 25 ns
80 T
SCH2DOV,
T
SCL2DOV
SDOx Data Output Valid after SCKx Edge — 50 ns
82 T
SSL2DOV SDOx Data Output Valid after SSx  Edge — 50 ns
83 T
SCH2SSH,
T
SCL2SSH
SSx
 after SCKx Edge 1.5 TCY + 40 — ns
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
SSx
SCKx
(CKPx =
0)
SCKx
(CKPx =
1)
SDOx
SDIx
70
71 72
82
74
75, 76
MSb bit 6 - - - - - - 1 LSb
77
bit 6 - - - - 1 LSb In
80
83
Note: Refer to Figure 31-3 for load conditions.
MSb In