Datasheet

 2009-2011 Microchip Technology Inc. DS39960D-page 421
PIC18F87K22 FAMILY
28.3 On-Chip Voltage Regulator
All of the PIC18F87K22 family devices power their core
digital logic at a nominal 3.3V. For designs that are
required to operate at a higher typical voltage, such as
5V, all family devices incorporate two on-chip regula-
tors that allow the device to run its core logic from V
DD.
Those regulators are:
• Normal On-Chip Regulator
• Ultra Low-Power On-Chip Regulator
The hardware configuration of these regulators is the
same and is explained in
Section 28.3.1 “Regulator
Enable/Disable By Hardware”
. The regulators’ only
differences relate to when the device enters Sleep, as
explained in
Section 28.3.2 “Operation of Regulator
in Sleep”
.
28.3.1 REGULATOR ENABLE/DISABLE BY
HARDWARE
The regulator can be enabled or disabled only by hard-
ware. The regulator is controlled by the ENVREG pin
and the V
DDCORE/VCAP pin.
28.3.1.1 Regulator Enable Mode
Tying VDD to the pin enables the regulator, which in turn,
provides power to the core from the other V
DD pins.
When the regulator is enabled, a low-ESR filter capac-
itor must be connected to the V
DDCORE/VCAP pin (see
Figure 28-2). This helps maintain the regulator’s
stability. The recommended value for the filter capacitor
is given in
Section 31.2 “DC Characteristics: Power-
Down and Supply Current PIC18F87K22 Family
(Industrial/Extended)”.
28.3.1.2 Regulator Disable Mode
If the regulator is disabled by connecting VSS to the
ENVREG pin, the power to the core is supplied directly
by V
DD. The voltage levels for VDD must not exceed the
specified V
DDCORE levels. In Regulator Disabled mode,
a 0.1 µF capacitor should be connected to the
V
DDCORE/VCAP pin (see Figure 28-2).
When the regulator is being used, the overall voltage
budget is very tight. The regulator should operate the
device down to 1.8V. When V
DD drops below 3.3V, the
regulator no longer regulates, but the output voltage fol-
lows the input until V
DD reaches 1.8V. Below this voltage,
the output of the regulator output may drop to 0V.
FIGURE 28-2: CONNECTIONS FOR THE
ON-CHIP REGULATOR
VDD
ENVREG
V
DDCORE/VCAP
VSS
CF
5V
Regulator Enabled (ENVREG tied to VDD):
VDD
ENVREG
V
DDCORE/VCAP
V
SS
3.3V
(1)
Regulator Disabled (ENVREG tied to VSS):
Note 1:
These are typical operating voltages. For the
full operating ranges of V
DD and VDDCORE,
see
Section 31.2 “DC Characteristics:
Power-Down and Supply Current
PIC18F87K22 Family (Industrial/
Extended)”
.
PIC18F87K22
PIC18F87K22
0.1µF