Datasheet

PIC18F87K22 FAMILY
DS39960D-page 410  2009-2011 Microchip Technology Inc.
REGISTER 28-6: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h)
R/P-1 U-0 U-0 U-0 R/P-1 U-0 R/P-1 R/P-1
MCLRE
— — — MSSPMSK —ECCPMX
(1)
CCP2MX
bit 7 bit 0
Legend: P = Programmable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7
MCLRE: MCLR Pin Enable bit
1 = MCLR pin is enabled; RG5 input pin is disabled
0 = RG5 input pin is enabled; MCLR is disabled
bit 6-4
Unimplemented: Read as ‘0’
bit 3
MSSPMSK: MSSP V3 7-Bit Address Masking Mode Enable bit
1 = 7-Bit Address Masking mode is enabled
0 = 5-Bit Address Masking mode is enabled
bit 2
Unimplemented: Read as ‘0’
bit 1
ECCPMX: ECCP MUX bit
(1)
1 =
- ECCP1 (P1B/P1C) is multiplexed onto RE6 and RE5, CCP6 onto RE6, and CCP7 onto RE5
- ECCP3 (P3B/P3C) is multiplexed onto RE4 and RE3, CCP8 onto RE4, and CCP9 onto RE3
0 =
- ECCP1 (P1B/P1C) is multiplexed onto RH7 and RH6, CCP6 onto RH7, and CCP7
(2)
onto RH6
- ECCP3 (P3B/P3C) is multiplexed onto RH5 and RH4, CCP8 onto RH5, and CCP9
(2)
onto RH4
bit 0
CCP2MX: ECCP2 MUX bit
1 = ECCP2 is multiplexed with RC1
0 = ECCP2 is multiplexed with RB3 in Extended Microcontroller mode; ECCP2 is multiplexed with
RE7 in Microcontroller mode
Note 1: Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’.
2: Not implemented on 32K devices (PIC18F65K22 and PIC18F85K22).