Datasheet

PIC18F87K22 FAMILY
DS39960D-page 374  2009-2011 Microchip Technology Inc.
24.7 Comparator Operation
During Sleep
When a comparator is active and the device is placed
in Sleep mode, the comparator remains active and the
interrupt is functional, if enabled. This interrupt will
wake up the device from Sleep mode, when enabled.
Each operational comparator will consume additional
current.
To minimize power consumption while in Sleep mode,
turn off the comparators (CON =
0) before entering
Sleep. If the device wakes up from Sleep, the contents
of the CMxCON register are not affected.
24.8 Effects of a Reset
A device Reset forces the CMxCON registers to their
Reset state. This forces both comparators and the
voltage reference to the OFF state.
TABLE 24-3: REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
PIR6
— — — EEIF — CMP3IF CMP2IF CMP1IF
PIE6
— — — EEIE — CMP3IE CMP2IE CMP1IE
IPR6
— — — EEIP — CMP3IP CMP2IP CMP1IP
CM1CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0
CM2CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0
CM3CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0
CVRCON CVREN CVROE CVRSS CVR4 CVR3 CVR2 CVR1 CVR0
CMSTAT CMP3OUT CMP2OUT CMP1OUT
— — — — —
PORTF
RF7 RF6 RF5 RF4 RF3 RF2 RF1 —
LATF
LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 —
TRISF
TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 —
PORTG
— — RG5
(1)
RG4 RG3 RG2 RG1 RG0
LATG
— — — LATG4 LATG3 LATG2 LATG1 LATG0
TRISG
— — — TRISG4 TRISG3 TRISG2 TRISG1 TRISG0
PORTH RH7 RH6 RH5 RH4
RH3 RH2 RH1 RH0
LATH LATH7 LATH6 LATH5 LATH4
LATH3 LATH2 LATH1 LATH0
TRISH TRISH7 TRISH6 TRISH5 TRISH4
TRISH3 TRISH2 TRISH1 TRISH0
ANCON0
ANSEL7 ANSEL6 ANSEL5 ANSEL4 ANSEL3 ANSEL2 ANSEL1 ANSEL0
ANCON1 ANSEL15 ANSEL14 ANSEL13 ANSEL12 ANSEL11 ANSEL10 ANSEL9 ANSEL8
ANCON2
ANSEL23 ANSEL22 ANSEL21 ANSEL20 ANSEL19 ANSEL18 ANSEL17 ANSEL16
PMD0
CCP3MD CCP2MD CCP1MD UART2MD UART1MD SSP2MD SSP1MD ADCMD
Legend: — = unimplemented, read as ‘0’.
Note 1: Bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, the bit is unimplemented.