Datasheet

 2009-2011 Microchip Technology Inc. DS39960D-page 361
PIC18F87K22 FAMILY
After the A/D module has been configured as desired,
the selected channel must be acquired before the
conversion can start. The analog input channels must
have their corresponding TRIS bits selected as inputs.
To determine acquisition time, see
Section 23.3 “A/D
Acquisition Requirements”
. After this acquisition
time has elapsed, the A/D conversion can be started.
An acquisition time can be programmed to occur
between setting the GO/DONE
bit and the actual start
of the conversion.
To do an A/D conversion, follow these steps:
1. Configure the A/D module:
• Configure the required ADC pins as analog
pins (ANCON0, ANCON1 and ANCON2)
• Set the voltage reference (ADCON1)
• Select the A/D positive and negative input
channels (ADCON0 and ADCON1)
• Select the A/D acquisition time (ADCON2)
• Select the A/D conversion clock (ADCON2)
• Turn on the A/D module (ADCON0)
2. Configure the A/D interrupt (if desired):
• Clear the ADIF bit (PIR1<6>)
• Set the ADIE bit (PIE1<6>)
• Set the GIE bit (INTCON<7>)
3. Wait the required acquisition time (if required).
4. Start the conversion:
• Set the GO/DONE
bit (ADCON0<1>)
5. Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE
bit to be cleared
OR
• Waiting for the A/D interrupt
6. Read A/D Result registers (ADRESH:ADRESL)
and, if required, clear bit, ADIF.
7. For the next conversion, begin with Step 1 or 2,
as required.
The A/D conversion time per bit is defined as T
AD.
Before the next acquisition starts, a minimum Wait
of 2 T
AD is required.
FIGURE 23-5: ANALOG INPUT MODEL
VAIN
CPIN
RS
ANx
5 pF
V
DD
VT = 0.6V
V
T = 0.6V
I
LEAKAGE
RIC 1k
Sampling
Switch
SS
R
SS
CHOLD = 25 pF
V
SS
Sampling Switch
1234
(k)
VDD
±100 nA
Legend: CPIN
VT
ILEAKAGE
RIC
SS
C
HOLD
= Input Capacitance
= Threshold Voltage
= Leakage Current at the pin due to
= Interconnect Resistance
= Sampling Switch
= Sample/Hold Capacitance (from DAC)
various junctions
= Sampling Switch ResistanceRSS