Datasheet

PIC18F87K22 FAMILY
DS39960D-page 36  2009-2011 Microchip Technology Inc.
PORTJ is a bidirectional I/O port.
RJ0/ALE
RJ0
ALE
62
I/O
O
ST
—
Digital I/O.
External memory address latch enable.
RJ1/OE
RJ1
OE
61
I/O
O
ST
—
Digital I/O.
External memory output enable.
RJ2/WRL
RJ2
WRL
60
I/O
O
ST
—
Digital I/O.
External memory write low control.
RJ3/W
RH
RJ3
W
RH
59
I/O
O
ST
—
Digital I/O.
External memory high control.
RJ4/BA0
RJ4
BA0
39
I/O
O
ST
—
Digital I/O.
External Memory Byte Address 0 control
RJ5/CE
RJ5
CE
40
I/O
O
ST
—
Digital I/O
External memory chip enable control.
RJ6/LB
RJ6
LB
41
I/O
O
ST
—
Digital I/O.
External memory low byte control.
RJ7/UB
RJ7
UB
42
I/O
O
ST
—
Digital I/O.
External memory high byte control.
VSS 11, 31, 51, 70 P — Ground reference for logic and I/O pins.
V
DD 32, 48, 71 P — Positive supply for logic and I/O pins.
AVSS 26 P — Ground reference for analog modules.
AVDD 25 P — Positive supply for analog modules.
ENVREG 24 I ST Enable for on-chip voltage regulator.
V
DDCORE/VCAP
VDDCORE
VCAP
12
P—
Core logic power or external filter capacitor connection.
External filter capacitor connection (regulator
enabled/disabled).
TABLE 1-4: PIC18F8XK22 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DD)
I
2
C= I
2
C™/SMBus
Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared.
3: Not available on PIC18F65K22 and PIC18F85K22 devices.
4: PSP is available only in Microcontroller mode.
5: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit
(CONFIG3H<1>).