Datasheet

 2009-2011 Microchip Technology Inc. DS39960D-page 313
PIC18F87K22 FAMILY
21.4.7 BAUD RATE
In I
2
C Master mode, the Baud Rate Generator (BRG)
reload value is placed in the lower 7 bits of the
SSPxADD register (Figure 21-19). When a write
occurs to SSPxBUF, the Baud Rate Generator will
automatically begin counting. The BRG counts down to
0 and stops until another reload has taken place. The
BRG count is decremented twice per instruction cycle
(T
CY) on the Q2 and Q4 clocks. In I
2
C Master mode, the
BRG is reloaded automatically.
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK
), the internal
clock will automatically stop counting and the SCLx pin
will remain in its last state.
Table 21-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPxADD. The SSPxADD BRG value of 0x00 is not
supported.
21.4.7.1 Baud Rate and Module
Interdependence
Because MSSP1 and MSSP2 are independent, they
can operate simultaneously in I
2
C Master mode at
different baud rates. This is done by using different
BRG reload values for each module.
Because this mode derives its basic clock source from
the system clock, any changes to the clock will affect
both modules in the same proportion. It may be
possible to change one or both baud rates back to a
previous value by changing the BRG reload value.
FIGURE 21-19: BAUD RATE GENERATOR BLOCK DIAGRAM
TABLE 21-3: I
2
C™ CLOCK RATE w/BRG
FOSC FCY FCY * 2 BRG Value
F
SCL
(2 Rollovers of BRG)
40 MHz 10 MHz 20 MHz 18h 400 kHz
40 MHz 10 MHz 20 MHz 1Fh 312.5 kHz
40 MHz 10 MHz 20 MHz 63h 100 kHz
16 MHz 4 MHz 8 MHz 09h 400 kHz
16 MHz 4 MHz 8 MHz 0Ch 308 kHz
16 MHz 4 MHz 8 MHz 27h 100 kHz
4 MHz 1 MHz 2 MHz 02h 333 kHz
4 MHz 1 MHz 2 MHz 09h 100 kHz
16 MHz 4 MHz 8 MHz 03h 1 MHz
(1)
Note 1: A minimum of 16 MHz FOSC is required to get 1 MHz I
2
C.
SSPM<3:0>
BRG Down Counter
CLKO
F
OSC/4
SSPxADD<6:0>
SSPM<3:0>
SCLx
Reload
Control
Reload