Datasheet

 2009-2011 Microchip Technology Inc. DS39960D-page 279
PIC18F87K22 FAMILY
20.4.8 OPERATION IN POWER-MANAGED
MODES
In Sleep mode, all clock sources are disabled.
Timer2/4/6/8 will not increment and the state of the
module will not change. If the ECCPx pin is driving a
value, it will continue to drive that value. When the
device wakes up, it will continue from this state. If
Two-Speed Start-ups are enabled, the initial start-up
frequency from HF-INTOSC and the postscaler may
not be immediately stable.
In PRI_IDLE mode, the primary clock will continue to
clock the ECCPx module without change.
20.4.8.1 Operation with Fail-Safe
Clock Monitor (FSCM)
If the Fail-Safe Clock Monitor (FSCM) is enabled, a clock
failure will force the device into the power-managed
RC_RUN mode and the OSCFIF bit of the PIR2 register
will be set. The ECCPx will then be clocked from the
internal oscillator clock source, which may have a
different clock frequency than the primary clock.
20.4.9 EFFECTS OF A RESET
Both Power-on Reset and subsequent Resets will force
all ports to Input mode and the ECCP registers to their
Reset states. This forces the ECCP module to reset to
a state compatible with previous, non-Enhanced CCP
modules used on other PIC18 and PIC16 devices.
TABLE 20-4: REGISTERS ASSOCIATED WITH ECCP1/2/3 MODULE AND
TIMER1/2/3/4/6/8/10/12
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
INTCON
GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
RCON IPEN
SBOREN CM RI TO PD POR BOR
PIR3 TMR5GIF — RC2IF TX2IF CTMUIF CCP2IF CCP1IF RTCCIF
PIR4 CCP10IF
(1)
CCP9IF
(1)
CCP8IF CCP7IF CCP6IF CCP5IF CCP4IF CCP3IF
PIE3 TMR5GIE — RC2IE TX2IE CTMUIE CCP2IE CCP1IE RTCCIE
PIE4 CCP10IE
(1)
CCP9IE
(1)
CCP8IE CCP7IE CCP6IE CCP5IE CCP4IE CCP3IE
IPR3 TMR5GIP — RC2IP TX2IP CTMUIP CCP2IP CCP1IP RTCCIP
IPR4 CCP10IP
(1)
CCP9IP
(1)
CCP8IP CCP7IP CCP6IP CCP5IP CCP4IP CCP3IP
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
TRISC TRISC7 TRISC6
TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0
TRISH
(2)
TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0
TMR1H Timer1 Register High Byte
TMR1L Timer1 Register Low Byte
TMR2 Timer2 Register
TMR3H Timer3 Register High Byte
TMR3L Timer3 Register Low Byte
TMR4 Timer4 Register
TMR6 Timer6 Register
TMR8 Timer8 Register
TMR10
(1)
TMR10 Register
TMR12
(1)
TMR10 Register
PR2 Timer2 Period Register
PR4 Timer4 Period Register
PR6 Timer6 Period Register
PR8 Timer8 Period Register
PR10
(1)
Timer10 Period Register
PR12
(1)
Timer12 Period Register
Note 1: Unimplemented on devices with a program memory of 32 Kbytes (PIC18F65K22 and PIC18F85K22).
2: Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’.