Datasheet

 2009-2011 Microchip Technology Inc. DS39960D-page 253
PIC18F87K22 FAMILY
FIGURE 19-2: COMPARE MODE OPERATION BLOCK DIAGRAM
TABLE 19-5: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1/3/5/7
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
RCON IPEN SBOREN CM RI TO PD POR BOR
PIR4 CCP10IF
(1)
CCP9IF
(1)
CCP8IF CCP7IF CCP6IF CCP5IF CCP4IF CCP3IF
PIE4 CCP10IE
(1)
CCP9IE
(1)
CCP8IE CCP7IE CCP6IE CCP5IE CCP4IE CCP3IE
IPR4 CCP10IP
(1)
CCP9IP
(1)
CCP8IP CCP7IP CCP6IP CCP5IP CCP4IP CCP3IP
TRISB
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
TRISC TRISC7
TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
TRISE
TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0
TRISH
(2)
TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0
TMR1L Timer1 Register Low Byte
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare or Timer1/3/5/7.
Note 1: Unimplemented on devices with a program memory of 32 Kbytes (PIC18F65K22 and PIC18F85K22).
2: Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’.
CCPR5H CCPR5L
TMR1H TMR1L
Comparator
QS
R
Output
Logic
Special Event Trigger
Set CCP5IF
CCP5 Pin
TRIS
CCP5CON<3:0>
Output Enable
TMR5H TMR5L
1
0
Compare
4
(Timer1/5 Reset)
Match
Note: This block diagram uses CCP4 and CCP5, and their appropriate timers as an example. For details on all of
the CCP modules and their timer assignments, see Table 19-2 and Table 19-3.
TMR1H TMR1L
TMR5H TMR5L
CCPR4H CCPR4L
Comparator
C4TSEL1
Set CCP4IF
1
0
QS
R
Output
Logic
Special Event Trigger
CCP4 Pin
TRIS
CCP4CON<3:0>
Output Enable
4
(Timer1/Timer3 Reset, A/D Trigger)
Compare
Match
C5TSEL0
C4TSEL0