Datasheet

 2009-2011 Microchip Technology Inc. DS39960D-page 219
PIC18F87K22 FAMILY
16.5.4 TIMER3/5/7 GATE SINGLE PULSE
MODE
When Timer3/5/7 Gate Single Pulse mode is enabled,
it is possible to capture a single pulse gate event.
Timer3/5/7 Gate Single Pulse mode is first enabled by
setting the TxGSPM bit (TxGCON<4>). Next, the
TxGGO/TxDONE
bit (TxGCON<3>) must be set.
The Timer3/5/7 will be fully enabled on the next incre-
menting edge. On the next trailing edge of the pulse,
the TxGGO/TxDONE
bit will automatically be cleared.
No other gate events will be allowed to increment
Timer3/5/7 until the TxGGO/TxDONE bit is once again
set in software.
Clearing the TxGSPM bit also will clear the TxGGO/
TxDONE
bit. (For timing details, see Figure 16-4.)
Simultaneously enabling the Toggle mode and the
Single Pulse mode will permit both sections to work
together. This allows the cycle times on the Timer3/5/7
gate source to be measured. (For timing details, see
Figure 16-5.)
FIGURE 16-4: TIMER3/5/7 GATE SINGLE PULSE MODE
TMRxGE
TxGPOL
TxG_IN
TxCKI
TxGVAL
Timer3/5/7
N N + 1 N + 2
TxGSPM
TxGGO/
TxDONE
Set by Software
Cleared by Hardware on
Falling Edge of TxGVAL
Set by Hardware on
Falling Edge of TxGVAL
Cleared by Software
Cleared by
Software
TMRxGIF
Counting Enabled on
Rising Edge of TxG