Datasheet

 2009-2011 Microchip Technology Inc. DS39960D-page 217
PIC18F87K22 FAMILY
16.5 Timer3/5/7 Gates
Timer3/5/7 can be configured to count freely or the count
can be enabled and disabled using the Timer3/5/7 gate
circuitry. This is also referred to as the Timer3/5/7 gate
count enable.
The Timer3/5/7 gate can also be driven by multiple
selectable sources.
16.5.1 TIMER3/5/7 GATE COUNT ENABLE
The Timerx Gate Enable mode is enabled by setting
the TMRxGE bit (TxGCON<7>). The polarity of the
Timerx Gate Enable mode is configured using the
TxGPOL bit (TxGCON<6>).
When Timerx Gate Enable mode is enabled, Timer3/5/7
will increment on the rising edge of the Timer3/5/7 clock
source. When Timerx Gate Enable mode is disabled, no
incrementing will occur and Timer3/5/7 will hold the
current count. See Figure 16-2 for timing details.
TABLE 16-1: TIMER3/5/7 GATE ENABLE
SELECTIONS
FIGURE 16-2: TIMER3/5/7 GATE COUNT ENABLE MODE
TxCLK
(†)
TxGPOL
(TxGCON<6>)
TxG Pin
Timerx
Operation
 00Counts
 01Holds Count
 10Holds Count
 11Counts
† The clock on which TMR3/5/7 is running. For
more information, see TxCLK in Figure 16-1.
TMRxGE
TxGPOL
TxG_IN
TxCKI
TxGVAL
Timer3/5/7
N N + 1 N + 2 N + 3 N + 4