Datasheet

 2009-2011 Microchip Technology Inc. DS39960D-page 19
PIC18F87K22 FAMILY
PORTD is a bidirectional I/O port.
RD0/PSP0/CTPLS
RD0
PSP0
CTPLS
58
I/O
I/O
O
ST
TTL
—
Digital I/O.
Parallel Slave Port data.
CTMU pulse generator output.
RD1/PSP1/T5CKI/T7G
RD1
PSP1
T5CKI
T7G
55
I/O
I/O
I
I
ST
TTL
ST
ST
Digital I/O.
Parallel Slave Port.
Timer5 clock input.
Timer7 external clock gate input.
RD2/PSP2
RD2
PSP2
54
I/O
O
ST
TTL
Digital I/O.
Parallel Slave Port.
RD3/PSP3
RD3
PSP3
53
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port.
RD4/PSP4/SDO2
RD4
PSP4
SDO2
52
I/O
I/O
O
ST
TTL
—
Digital I/O.
Parallel Slave Port.
SPI data out.
RD5/PSP5/SDI2/SDA2
RD5
PSP5
SDI2
SDA2
51
I/O
I/O
I
I/O
ST
TTL
ST
I
2
C
Digital I/O.
Parallel Slave Port.
SPI data in.
I
2
C™ data I/O.
RD6/PSP6/SCK2/SCL2
RD6
PSP6
SCK2
SCL2
(4)
50
I/O
I/O
I/O
I/O
ST
TTL
ST
I
2
C
Digital I/O.
Parallel Slave Port.
Synchronous serial clock.
Synchronous serial clock I/O for I
2
C mode.
RD7/PSP7/SS2
RD7
PSP7
SS2
49
I/O
I/O
I
ST
TTL
TTL
Digital I/O.
Parallel Slave Port.
SPI slave select input.
TABLE 1-3: PIC18F6XK22 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
QFN/TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DD)
I
2
C= I
2
C™/SMBus
Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared.
3: Not available on PIC18F65K22 and PIC18F85K22 devices.
4: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit
(CONFIG3H<1>).