Datasheet

PIC18F87K22 FAMILY
DS39960D-page 184  2009-2011 Microchip Technology Inc.
TABLE 12-14: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG
RG2/RX2/DT2/
AN18/C3INA
RG2 0 O DIG LATG<2> data output.
1 I ST PORTG<2> data input.
RX2 1 I ST Asynchronous serial receive data input (EUSART module).
DT2 1 O DIG Synchronous serial data output (EUSART module); takes priority over
port data.
1 I ST Synchronous serial data input (EUSART module); user must configure
as an input.
AN18 1 I ANA A/D Input Channel 18.
Default input configuration on POR; does not affect digital output.
C3INA x I ANA Comparator 3 Input A.
RG3/CCP4/AN17/
P3D/C3INB
RG3 0 O DIG LATG<3> data output.
1 I ST PORTG<3> data input.
CCP4 0 O DIG CCP4 compare/PWM output; takes priority over port data.
1 I ST CCP4 capture input.
AN17 1 I ANA A/D Input Channel 17.
Default input configuration on POR; does not affect digital output.
P3D 0 O — ECCP3 PWM Output D.
May be configured for tri-state during Enhanced PWM.
C3INB x I ANA Comparator 3 Input B.
RG4/RTCC/
T7CKI/T5G/
CCP5/AN16/
P1D/C3INC
RG4 0 O DIG LATG<4> data output.
1 I ST PORTG<4> data input.
RTCC x O DIG RTCC output.
T7CKI x I ST Timer7 clock input.
T5G x I ST Timer5 external clock gate input.
CCP5 0 O DIG CCP5 compare/PWM output; takes priority over port data.
1 I ST CCP5 capture input.
AN16 1 I ANA A/D Input Channel 17.
Default input configuration on POR; does not affect digital output.
P1D 0 O — ECCP1 PWM Output D.
May be configured for tri-state during Enhanced PWM.
C3INC x I ANA Comparator 3 Input C.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PORTG
— —RG5
(2)
RG4 RG3 RG2 RG1 RG0
TRISG
— — — TRISG4 TRISG3 TRISG2 TRISG1 TRISG0
ANCON2
ANSEL23 ANSEL22 ANSEL21 ANSEL20 ANSEL19 ANSEL18 ANSEL17 ANSEL16
ODCON1 SSP1OD CCP2OD CCP1OD — — — — SSP2OD
ODCON2
CCP10OD
(1)
CCP9OD
(1)
CCP8OD CCP7OD CCP6OD CCP5OD CCP4OD CCP3OD
ODCON3 U2OD
U1OD — — — — — CTMUDS
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTG.
Note 1: Unimplemented on PIC18FX5K22 devices, read as ‘0’.
2: This bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, the bit is
unimplemented.
TABLE 12-13: PORTG FUNCTIONS (CONTINUED)
Pin Name Function
TRIS
Setting
I/O
I/O
Type
Description
Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).