Datasheet

 2009-2011 Microchip Technology Inc. DS39960D-page 181
PIC18F87K22 FAMILY
12.7 PORTF, LATF and TRISF Registers
PORTF is a 7-bit wide, bidirectional port. The
corresponding Data Direction and Output Latch registers
are TRISF and LATF. All pins on PORTF are
implemented with Schmitt Trigger input buffers. Each pin
is individually configurable as an input or output.
Pins, RF1 through RF6, may be used as comparator
inputs or outputs by setting the appropriate bits in the
CMCON register. To use RF<7:1> as digital inputs, it is
also necessary to turn off the comparators.
EXAMPLE 12-6: INITIALIZING PORTF
Note 1: On device Resets, pins, RF<7:1>, are
configured as analog inputs and are read
as ‘0’.
2: To configure PORTF as a digital I/O, turn
off the comparators and clear ANCON1
and ANCON2 to digital.
CLRF PORTF ; Initialize PORTF by
; clearing output
; data latches
CLRF LATF ; Alternate method
; to clear output
; data latches
BANKSEL ANCON1 ; Select bank with ANCON1 register
MOVLW 1Fh ; Make AN6, AN7 and AN5 digital
MOVWF ANCON1 ;
MOVLW 0Fh ; Make AN8, AN9, AN10 and AN11
digital
MOVWF ANCON ; Set PORTF as digital I/O
BANKSEL TRISF ; Select bank with TRISF register
MOVLW 0CEh ; Value used to
; initialize data
; direction
MOVWF TRISF ; Set RF3:RF1 as inputs
; RF5:RF4 as outputs
; RF7:RF6 as inputs
TABLE 12-11: PORTF FUNCTIONS
Pin Name Function
TRIS
Setting
I/O
I/O
Type
Description
RF1/AN6/C2OUT/
CTDIN
RF1 0 O DIG LATF<1> data output; not affected by analog input.
1 I ST PORTF<1> data input; disabled when analog input is enabled.
AN6 1 I ANA A/D Input Channel 6. Default configuration on POR.
C2OUT 0 O DIG Comparator 2 output; takes priority over port data.
CTDIN 1 I ST CTMU pulse delay input.
RF2/AN7/C1OUT RF2 0 O DIG LATF<2> data output; not affected by analog input.
1 I ST PORTF<2> data input; disabled when analog input is enabled.
AN7 1 I ANA A/D Input Channel 7. Default configuration on POR.
C1OUT 0 O DIG Comparator 1 output; takes priority over port data.
RF3/AN8/C2INB/
CTMUI
RF3 0 O DIG LATF<3> data output; not affected by analog input.
1 I ST PORTF<3> data input; disabled when analog input is enabled.
AN8 1 I ANA A/D Input Channel 8 and Comparator C2+ input. Default input
configuration on POR; not affected by analog output.
C2INB 1 I ANA Comparator 2 Input B.
CTMUI x O — CTMU pulse generator charger for the C2INB comparator input.
RF4/AN9/C2INA RF4 0 O DIG LATF<4> data output; not affected by analog input.
1 I ST PORTF<4> data input; disabled when analog input is enabled.
AN9 1 I ANA A/D Input Channel 9 and Comparator C2- input. Default input
configuration on POR; does not affect digital output.
C2INA 1 I ANA Comparator 2 Input A.
RF5/AN10/CV
REF/
C1INB
RF5 0 O DIG LATF<5> data output; not affected by analog input. Disabled when
CV
REF output is enabled.
1 I ST PORTF<5> data input; disabled when analog input is enabled.
Disabled when CV
REF output is enabled.
AN10 1 I ANA A/D Input Channel 10 and Comparator C1+ input. Default input
configuration on POR.
CV
REF x O ANA Comparator voltage reference output. Enabling this feature disables
digital I/O.
C1INB 1 I ANA Comparator 1 Input B.
Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).