Datasheet

PIC18F87K22 FAMILY
DS39960D-page 156  2009-2011 Microchip Technology Inc.
REGISTER 11-15: PIE6: PERIPHERAL INTERRUPT ENABLE REGISTER 6
U-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
— — — EEIE — CMP3IE CMP2IE CMP1IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 Unimplemented: Read as ‘0’
bit 4 EEIE: Data EEDATA/Flash Write Operation Enable bit
1 = Interrupt is enabled
0 = interrupt is disabled
bit 3 Unimplemented: Read as ‘0’
bit 2 CMP3IE: CMP3 Enable bit
1 = Interrupt is enabled
0 = interrupt is disabled
bit 1 CMP2E: CMP2 Enable bit
1 = Interrupt is enabled
0 = interrupt is disabled
bit 0 CMP1IE: CMP1 Enable bit
1 = Interrupt is enabled
0 = interrupt is disabled