Datasheet

PIC18F87K22 FAMILY
DS39960D-page 154  2009-2011 Microchip Technology Inc.
REGISTER 11-12: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
R/W-0 U-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
TMR5GIE
— RC2IE TX2IE CTMUIE CCP2IE CCP1IE RTCCIE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 TMR5GIE: Timer5 Gate Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 6 Unimplemented: Read as ‘0’
bit 5 RC2IE: EUSART Receive Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 4 TX2IE: EUSART Transmit Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 3 CTMUIE: CTMU Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 2 CCP2IE: ECCP2 Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 1 CCP1IE: ECCP1 Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 0 RTCCIE: RTCC Interrupt Enable bit
1 = Enabled
0 = Disabled
REGISTER 11-13: PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CCP10IE
(1)
CCP9IE
(1)
CCP8IE CCP7IE CCP6IE CCP5IE CCP4IE CCP3IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 CCP<10:3>IE: CCP<10:3> Interrupt Enable bits
(1)
1 = Enabled
0 =Disabled
Note 1: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22).