Datasheet

PIC18F87K22 FAMILY
DS39960D-page 14  2009-2011 Microchip Technology Inc.
FIGURE 1-2: PIC18F8XK22 (80-PIN) BLOCK DIAGRAM
Instruction
Decode and
Control
Data Latch
Address Latch
Data Address<12>
12
Access
BSR
FSR0
FSR1
FSR2
inc/dec
logic
Address
4124
PCH PCL
PCLATH
8
31-Level Stack
Program Counter
PRODLPRODH
8 x 8 Multiply
8
BITOP
8
8
ALU<8>
Address Latch
Program Memory
Data Latch
20
8
8
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
3
PCLATU
PCU
W
Instruction Bus <16>
STKPTR
Bank
8
State Machine
Control Signals
Decode
8
8
ROM Latch
OSC1/CLKI
OSC2/CLKO
V
DD,VSS
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Precision
Reference
Band Gap
Regulator
Voltage
VDDCORE/VCAP
ENVREG
PORTA
PORTC
PORTD
PORTE
PORTF
PORTG
RA0:RA7
(1,2)
RC0:RC7
(1)
RD0:RD7
(1)
RF1:RF7
(1)
RG0:RG5
(1)
PORTB
RB0:RB7
(1)
PORTH
RH0:RH7
(1)
PORTJ
RJ0:RJ7
(1)
Note 1: See Table 1-3 for I/O port pin descriptions.
2: RA6 and RA7 are only available as digital I/O in select oscillator modes. See Section 3.0 “Oscillator Configurations” for
more information.
3: Unimplemented on the PIC18F85K22.
Timing
Generation
INTRC
Oscillator
16 MHz
Oscillator
RE0:RE7
(1)
BOR and
LVD
Data Memory
(2/4 Kbytes)
EUSART1
Comparator
MSSP1/2
3/5/7
(3)
2/4/6/8/10
(3)
/12
(3)
CTMUTimer1
ADC
12-Bit
EUSART2
Timer0
4/5/6/7/8/9
(3)
/10
(3)
RTCC
Timer
Timer
1/2/3
CCP
ECCP
1/2/3
System Bus Interface
AD15:0, A19:16
(Multiplexed with PORTD,
PORTE and PORTH)