Datasheet

 2009-2011 Microchip Technology Inc. DS39960D-page 131
PIC18F87K22 FAMILY
8.8 Operation in Power-Managed
Modes
In alternate, power-managed Run modes, the external
bus continues to operate normally. If a clock source
with a lower speed is selected, bus operations will run
at that speed. In these cases, excessive access times
for the external memory may result if Wait states have
been enabled and added to external memory opera-
tions. If operations in a lower power Run mode are
anticipated, users should provide in their applications
for adjusting memory access times at the lower clock
speeds.
In Sleep and Idle modes, the microcontroller core does
not need to access data; bus operations are
suspended. The state of the external bus is frozen, with
the address/data pins, and most of the control pins,
holding at the same state they were in when the mode
was invoked. The only potential changes are to the CE
,
LB
and UB pins, which are held at logic high.
TABLE 8-3: REGISTERS ASSOCIATED WITH THE EXTERNAL MEMORY BUS
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MEMCON
(1)
EBDIS —WAIT1WAIT0— —WM1WM0
PADCFG1 RDPU REPU RJPU
(1)
— — RTSECSEL1 RTSECSEL0 —
PMD1
PSPMD CTMUMD RTCCMD TMR4MD TMR3MD TMR2MD TMR1MD EMBMD
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during External Memory Bus access.
Note 1: Unimplemented in 64-pin devices (PIC18F6XK22), read as ‘0’.