Datasheet

 2009-2011 Microchip Technology Inc. DS39960D-page 13
PIC18F87K22 FAMILY
FIGURE 1-1: PIC18F6XK22 (64-PIN) BLOCK DIAGRAM
Instruction
Decode and
Control
PORTA
Data Latch
Data Memory
(2/4 Kbytes)
Address Latch
Data Address<12>
12
Access
BSR
FSR0
FSR1
FSR2
inc/dec
logic
Address
4
12
4
PCH PCL
PCLATH
8
31-Level Stack
Program Counter
PRODLPRODH
8 x 8 Multiply
8
BITOP
8
8
ALU<8>
Address Latch
Program Memory
Data Latch
20
8
8
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
3
PCLATU
PCU
Note 1: See Table 1-3 for I/O port pin descriptions.
2: RA6 and RA7 are only available as digital I/O in select oscillator modes. For more information, see Section 3.0 “Oscillator
Configurations”.
3: Unimplemented on the PIC18F65K22.
EUSART1
Comparator
MSSP1/2
3/5/7
(3)
2/4/6/8/10
(3)
/12
(3)
CTMUTimer1
ADC
12-Bit
W
Instruction Bus <16>
STKPTR
Bank
8
State Machine
Control Signals
Decode
8
8
EUSART2
ROM Latch
PORTC
PORTD
PORTE
PORTF
PORTG
RA0:RA7
(1,2)
RC0:RC7
(1)
RD0:RD7
(1)
RE0: RE7
(1)
RF1:RF7
(1)
RG0:RG5
(1)
PORTB
RB0:RB7
(1)
OSC1/CLKI
OSC2/CLKO
V
DD,
Timing
Generation
V
SS
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
BOR and
LVD
Precision
Reference
Band Gap
INTRC
Oscillator
Regulator
Voltage
VDDCORE/VCAP
ENVREG
16 MHz
Oscillator
Timer0
4/5/6/7/8/9
(3)
/10
(3)
RTCC
Timer
Timer
1/2/3
CCP
ECCP
1/2/3