Datasheet

 2009-2011 Microchip Technology Inc. DS39960D-page 103
PIC18F87K22 FAMILY
F2Ch CCPTMRS1 C7TSEL1 C7TSEL0 — C6TSEL0 — C5TSEL0 C4TSEL1 C4TSEL0 00-0 -000
F2Bh CCPTMRS2
— — — C10TSEL0
(3)
— C9TSEL0
(3)
C8TSEL1 C8TSEL0 ---0 -000
F2Ah REFOCON ROON
— ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 0-00 0000
F29h ODCON1 SSP1OD CCP2OD CCP1OD
— — — — SSP2OD 000- ---0
F28h ODCON2 CCP10OD
(3)
CCP9OD
(3)
CCP8OD CCP7OD CCP6OD CCP5OD CCP4OD CCP3OD 0000 0000
F27h ODCON3 U2OD U1OD
— — — — — CTMUDS 00-- ---0
F26h MEMCON
(2)
EBDIS —WAIT1WAIT0 — —WM1WM00-00 --00
F25h ANCON0 ANSEL7 ANSEL6 ANSEL5 ANSEL4 ANSEL3 ANSEL2 ANSEL1 ANSEL0 1111 1111
F24h ANCON1 ANSEL15 ANSEL14 ANSEL13 ANSEL12 ANSEL11 ANSEL10 ANSEL9 ANSEL8 1111 1111
F23h ANCON2 ANSEL23 ANSEL22 ANSEL21 ANSEL20 ANSEL19 ANSEL18 ANSEL17 ANSEL16 1111 1111
F22h RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x
F21h TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010
F20h BAUDCON2 ABDOVF RCIDL RXDTP TXCKP BRG16
— WUE ABDEN 0100 0-00
F1Fh SPBRGH2 USART2 Baud Rate Generator High Byte 0000 0000
F1Eh SPBRG2 USART2 Baud Rate Generator 0000 0000
F1Dh RCREG2 Receive Data FIFO 0000 0000
F1Ch TXREG2 Transmit Data FIFO xxxx xxxx
F1Bh PSTR2CON CMPL1 CMPL0
— STRSYNC STRD STRC STRB STRA 00-0 0001
F1Ah PSTR3CON CMPL1 CMPL0
— STRSYNC STRD STRC STRB STRA 00-0 0001
F19h PMD0 CCP3MD CCP2MD CCP1MD UART2MD UART1MD SSP2MD SSP1MD ADCMD 0000 0000
F18h PMD1 PSPMD CTMUMD RTCCMD TMR4MD TMR3MD TMR2MD TMR1MD EMBMD 0000 0000
F17h PMD2 TMR10MD
(3)
TMR8MD TMR7MD
(3)
TMR6MD TMR5MD CMP3MD CMP2MD CMP1MD 0000 0000
F16h PMD3 CCP10MD
(3)
CCP9MD
(3)
CCP8MD CCP7MD CCP6MD CCP5MD CCP4MD TMR12MD
(3)
0000 0000
TABLE 6-2: PIC18F87K22 FAMILY REGISTER FILE SUMMARY (CONTINUED)
Address File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Note 1: This bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, the bit is unimplemented.
2: Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’.
3: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22).