Datasheet
PIC18F87K22 FAMILY
DS39960D-page 102 2009-2011 Microchip Technology Inc.
F5Ch RTCVALL RTCC Value Low Register Window Based on RTCPTR<1:0> 0000 0000
F5Bh ALRMCFG ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 0000 0000
F5Ah ALRMRPT ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 0000 0000
F59h ALRMVALH Alarm Value High Register Window Based on APTR<1:0> xxxx xxxx
F58h ALRMVALL Alarm Value Low Register Window Based on APTR<1:0> xxxx xxxx
F57h CTMUCONH CTMUEN
— CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG 0-00 0000
F56h CTMUCONL EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT 0000 0000
F55h CTMUICONH ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 0000 0000
F54h CM1CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 0001 1111
F53h PADCFG1 RDPU REPU RJPU
(2)
— — RTSECSEL1 RTSECSEL0 — 000- -00-
F52h ECCP2AS ECCP2ASE ECCP2AS2 ECCP2AS1 ECCP2AS0 PSS2AC1 PSS2AC0 PSS2BD1 PSS2BD0 0000 0000
F51h ECCP2DEL P2RSEN P2DC6 P2DC5 P2DC4 P2DC3 P2DC2 P2DC1 P2DC0 0000 0000
F50h CCPR2H Capture/Compare/PWM Register 2 High Byte xxxx xxxx
F4Fh CCPR2L Capture/Compare/PWM Register 2 Low Byte xxxx xxxx
F4Eh CCP2CON P2M1 P2M0 DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 0000 0000
F4Dh ECCP3AS ECCP3ASE ECCP3AS2 ECCP3AS1 ECCP3AS0 PSS3AC1 PSS3AC0 PSS3BD1 PSS3BD0 0000 0000
F4Ch ECCP3DEL P3RSEN P3DC6 P3DC5 P3DC4 P3DC3 P3DC2 P3DC1 P3DC0 0000 0000
F4Bh CCPR3H Capture/Compare/PWM Register 3 High Byte xxxx xxxx
F4Ah CCPR3L Capture/Compare/PWM Register 3 Low Byte xxxx xxxx
F49h CCP3CON P3M1 P3M0 DC3B1 DC3B0 CCP3M3 CCP3M2 CCP3M1 CCP3M0 0000 0000
F48h CCPR8H Capture/Compare/PWM Register 8 High Byte xxxx xxxx
F47h CCPR8L Capture/Compare/PWM Register 8 Low Byte xxxx xxxx
F46h CCP8CON
— — DC8B1 DC8B0 CCP8M3 CCP8M2 CCP8M1 CCP8M0 --00 0000
F45h CCPR9H
(3)
Capture/Compare/PWM Register 9 High Byte xxxx xxxx
F44h CCPR9L
(3)
Capture/Compare/PWM Register 9 Low Byte xxxx xxxx
F43h CCP9CON
(3)
— — DC9B1 DC9B0 CCP9M3 CCP9M2 CCP9M1 CCP9M0 --00 0000
F42h CCPR10H
(3)
Capture/Compare/PWM Register 10 High Byte xxxx xxxx
F41h CCPR10L
(3)
Capture/Compare/PWM Register 10 Low Byte xxxx xxxx
F40h CCP10CON
(3)
— — DC10B1 DC10B0 CCP10M3 CCP10M2 CCP10M1 CCP10M0 --00 0000
F3Fh TMR7H
(3)
Timer7 Register High Byte xxxx xxxx
F3Eh TMR7L
(3)
Timer7 Register Low Byte 0000 0000
F3Dh T7CON
(3)
TMR7CS1 TMR7CS0 T7CKPS1 T7CKPS0 SOSCEN T7SYNC RD16 TMR7ON 0000 0000
F3Ch T7GCON
(3)
TMR7GE T7GPOL T7GTM T7GSPM T7GGO/
T7DONE
T7GVAL T7GSS1 T7GSS0 0000 0x00
F3Bh TMR6 Timer6 Register 0000 0000
F3Ah PR6 Timer6 Period Register 1111 1111
F39h T6CON
— T6OUTPS3 T6OUTPS2 T6OUTPS1 T6OUTPS0 TMR6ON T6CKPS1 T6CKPS0 -000 0000
F38h TMR8 Timer8 Register 0000 0000
F37h PR8 Timer8 Period Register 1111 1111
F36h T8CON
— T8OUTPS3 T8OUTPS2 T8OUTPS1 T8OUTPS0 TMR8ON T8CKPS1 T8CKPS0 -000 0000
F35h TMR10
(3)
TMR10 Register 0000 0000
F34h PR10
(3)
Timer10 Period Register 1111 1111
F33h T10CON
(3)
—
T10OUTPS3 T10OUTPS2 T10OUTPS1 T10OUTPS0 TMR10ON T10CKPS1 T10CKPS0
-000 0000
F32h TMR12
(3)
TMR12 Register 0000 0000
F31h PR12
(3)
Timer12 Period Register 1111 1111
F30h T12CON
(3)
—
T12OUTPS3 T12OUTPS2 T12OUTPS1 T12OUTPS0
TMR12ON T12CKPS1 T12CKPS0 -000 0000
F2Fh CM2CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 0001 1111
F2Eh CM3CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 0001 1111
F2Dh CCPTMRS0 C3TSEL1 C3TSEL0 C2TSEL2 C2TSEL1 C2TSEL0 C1TSEL2 C1TSEL1 C1TSEL0 0000 0000
TABLE 6-2: PIC18F87K22 FAMILY REGISTER FILE SUMMARY (CONTINUED)
Address File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Note 1: This bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, the bit is unimplemented.
2: Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’.
3: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22).