Datasheet

 2009-2011 Microchip Technology Inc. DS39960D-page 101
PIC18F87K22 FAMILY
F86h PORTG — —RG5
(1)
RG4 RG3 RG2 RG1 RG0 --xx xxxx
F85h PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1
— xxxx xxx-
F84h PORTE RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 xxxx xxxx
F83h PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx
F82h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx
F81h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx
F80h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx xxxx
F7Fh EECON1 EEPGD CFGS
— FREE WRERR WREN WR RD xx-0 x000
F7Eh EECON2 EEPROM Control Register 2 (not a physical register) ---- ----
F7Dh TMR5H Timer5 Register High Byte xxxx xxxx
F7Ch TMR5L Timer5 Register Low Byte xxxx xxxx
F7Bh T5CON TMR5CS1 TMR5CS0 T5CKPS1 T5CKPS0 SOSCEN T5SYNC
RD16 TMR5ON 0000 0000
F7Ah T5GCON TMR5GE T5GPOL T5GTM T5GSPM T5GGO/
T5DONE
T5GVAL T5GSS1 T5GSS0 0000 0x00
F79h CCPR4H Capture/Compare/PWM Register 4 High Byte xxxx xxxx
F78h CCPR4L Capture/Compare/PWM Register 4 Low Byte xxxx xxxx
F77h CCP4CON
— — DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 --00 0000
F76h CCPR5H Capture/Compare/PWM Register 5 High Byte xxxx xxxx
F75h CCPR5L Capture/Compare/PWM Register 5 Low Byte xxxx xxxx
F74h CCP5CON
— — DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 --00 0000
F73h CCPR6H Capture/Compare/PWM Register 6 High Byte xxxx xxxx
F72h CCPR6L Capture/Compare/PWM Register 6 Low Byte xxxx xxxx
F71h CCP6CON
— — DC6B1 DC6B0 CCP6M3 CCP6M2 CCP6M1 CCP6M0 --00 0000
F70h CCPR7H Capture/Compare/PWM Register 7 High Byte xxxx xxxx
F6Fh CCPR7L Capture/Compare/PWM Register 7 Low Byte xxxx xxxx
F6Eh CCP7CON
— — DC7B1 DC7B0 CCP7M3 CCP7M2 CCP7M1 CCP7M0 --00 0000
F6Dh TMR4 Timer4 Register xxxx xxxx
F6Ch PR4 Timer4 Period Register 1111 1111
F6Bh T4CON
— T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 -111 1111
F6Ah SSP2BUF MSSP Receive Buffer/Transmit Register xxxx xxxx
F69h SSP2ADD MSSP Address Register in I
2
C™ Slave Mode. MSSP1 Baud Rate Reload Register in I
2
C Master Mode. 0000 0000
F68h SSP2STAT SMP CKE D/A
PSR/WUA BF 0000 0000
F67h SSP2CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000
F66h SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0100 0000
F65h BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16
— WUE ABDEN 0100 0-00
F64h OSCCON2
— SOSCRUN — —SOSCGO— MFIOFS MFIOSEL -0-- 0-x0
F63h EEADRH EEPROM Address Register High Byte 0000 0000
F62h EEADR EEPROM Address Register Low Byte 0000 0000
F61h EEDATA EEPROM Data Register 0000 0000
F60h PIE6
— — —EEIE— CMP3IE CMP2IE CMP1IE ---0 -000
F5Fh RTCCFG RTCEN
— RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR1 RTCPTR0 0-00 0000
F5Eh RTCCAL CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 0000 0000
F5Dh RTCVALH RTCC Value High Register Window Based on RTCPTR<1:0> xxxx xxxx
TABLE 6-2: PIC18F87K22 FAMILY REGISTER FILE SUMMARY (CONTINUED)
Address File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Note 1: This bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, the bit is unimplemented.
2: Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’.
3: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22).