Datasheet

PIC18F87K22 FAMILY
DS39960D-page 100  2009-2011 Microchip Technology Inc.
FB6h PIE4 CCP10IE
(3)
CCP9IE
(3)
CCP8IE CCP7IE CCP6IE CCP5IE CCP4IE CCP3IE 0000 0000
FB5h CVRCON CVREN CVROE CVRSS CVR4 CVR3 CVR2 CVR1 CVR0 0000 0000
FB4h CMSTAT CMP3OUT CMP2OUT CMP1OUT
— — — — — xxx- ----
FB3h TMR3H Timer3 Register High Byte xxxx xxxx
FB2h TMR3L Timer3 Register Low Byte xxxx xxxx
FB1h T3CON TMR3CS1 TMR3CS0 T3CKPS1 T3CKPS0 SOSCEN T3SYNC
RD16 TMR3ON 0000 0000
FB0h T3GCON TMR3GE T3GPOL T3GTM T3GSPM T3GGO/
T3DONE
T3GVAL T3GSS1 T3GSS0 0000 0x00
FAFh SPBRG1 USART1 Baud Rate Generator 0000 0000
FAEh RCREG1 USART1 Receive Register 0000 0000
FADh TXREG1 USART1 Transmit Register xxxx xxxx
FACh TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010
FABh RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x
FAAh T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/
T1DONE
T1GVAL T1GSS1 T1GSS0 0000 0x00
FA9h IPR6
— — — EEIP — CMP3IP CMP2IP CMP1IP ---1 -111
FA8h HLVDCON VDIRMAG BGVST IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 0000 0000
FA7h PSPCON IBF OBF IBOV PSPMODE
— — — — 0000 ----
FA6h PIR6
— — —EEIF— CMP3IF CMP2IF CMP1IF ---0 -000
FA5h IPR3 TMR5GIP
— RC2IP TX2IP CTMUIP CCP2IP CCP1IP RTCCIP 1-11 1111
FA4h PIR3 TMR5GiF
— RC2IF TX2IF CTMUIF CCP2IF CCP1IF RTCCIF 0-00 0000
FA3h PIE3 TMR5GIE
— RC2IE TX2IE CTMUIE CCP2IE CCP1IE RTCCIE 0-00 0000
FA2h IPR2 OSCFIP
— SSP2IP BCL2IP BCL1IP HLVDIP TMR3IP TMR3GIP 1-11 1111
FA1h PIR2 OSCFIF
— SSP2IF BCL2IF BCL1IF HLVDIF TMR3IF TMR3GIF 0-00 0000
FA0h PIE2 OSCFIE
— SSP2IE BCL2IE BCL1IE HLVDIE TMR3IE TMR3GIE 0-00 0000
F9Fh IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP TMR1GIP TMR2IP TMR1IP 1111 1111
F9Eh PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF TMR1GIF TMR2IF TMR1IF 0000 0000
F9Dh PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE TMR1GIE TMR2IE TMR1IE 0000 0000
F9Ch PSTR1CON CMPL1 CMPL0
— STRSYNC STRD STRC STRB STRA 00-0 0001
F9Bh OSCTUNE INTSRC PLLEN TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 0000 0000
F9Ah TRISJ
(2)
TRISJ7 TRISJ6 TRISJ5 TRISJ4 TRISJ3 TRISJ2 TRISJ1 TRISJ0 1111 1111
F99h TRISH
(2)
TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 1111 1111
F98h TRISG
— — — TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 ---1 1111
F97h TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1
— 1111 111-
F96h TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1
— 1111 111-
F95h TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111
F94h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111
F93h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111
F92h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111
F91h LATJ
(2)
LATJ7 LATJ6 LATJ5 LATJ4 LATJ3 LATJ2 LATJ1 LATJ0 xxxx xxxx
F90h LATH
(2)
LATH7 LATH6 LATH5 LATH4 LATH3 LATH2 LATH1 LATH0 xxxx xxxx
F8Fh LATG
— — — LATG4 LATG3 LATG2 LATG1 LATG0 ---x xxxx
F8Eh LATF LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1
— xxxx xxx-
F8Dh LATE LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 xxxx xxxx
F8Ch LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx xxxx
F8Bh LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx
F8Ah LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx xxxx
F89h LATA LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 xxxx xxxx
F88h PORTJ
(2)
RJ7 RJ6 RJ5 RJ4 RJ3 RJ2 RJ1 RJ0 xxxx xxxx
F87h PORTH
(2)
RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0 xxxx xxxx
TABLE 6-2: PIC18F87K22 FAMILY REGISTER FILE SUMMARY (CONTINUED)
Address File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Note 1: This bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, the bit is unimplemented.
2: Unimplemented on 64-pin devices (PIC18F6XK22), read as ‘0’.
3: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22).