PIC18F87K22 Family Data Sheet 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology 2009-2011 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC18F87K22 FAMILY 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash MCUs with 12-Bit A/D and nanoWatt XLP Technology Low-Power Features: Special Microcontroller Features: • Power-Managed modes: - Run: CPU on, peripherals on - Idle: CPU off, peripherals on - Sleep: CPU off, peripherals off • Two-Speed Oscillator Start-up • Fail-Safe Clock Monitor • Power-Saving Peripheral Module Disable (PMD) • Ultra Low-Power Wake-up • Fast Wake-up, 1 s Typical • Low-Power WDT, 300 nA Typical • Ultra Low 50 nA Input Le
PIC18F87K22 FAMILY Peripheral Highlights: • Up to Ten CCP/ECCP modules: - Up to seven Capture/Compare/PWM (CCP) modules - Three Enhanced Capture/Compare/PWM (ECCP) modules • Up to Eleven 8/16-Bit Timer/Counter modules: - Timer0 – 8/16-bit timer/counter with 8-bit programmable prescaler - Timer1,3 – 16-bit timer/counter - Timer2,4,6,8 – 8-bit timer/counter - Timer5,7 – 16-bit timer/counter for 64k and 128k parts - Timer10,12 – 8-bit timer/counter for 64k and 128k parts • Three Analog Comparators • Configurab
PIC18F87K22 FAMILY Pin Diagrams – PIC18F6XK22 RD7/PSP7/SS2 RD6/PSP6/SCK2/SCL2 RD5/PSP5/SDI2/SDA2 RD4/PSP4/SDO2 RD3/PSP3 RD2/PSP2 RD1/PSP1/T5CKI/T7G VSS VDD RD0/PSP0/CTPLS RE7/ECCP2/P2A RE6/P1B/CCP6 RE5/P1C/CCP7 RE3/P3C/CCP9(2)/REF0 RE4/P3B/CCP8 RE2/CS/P2B/CCP10(2) 64-Pin TQFP, QFN 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RE1/WR/P2C RE0/RD/P2D 1 48 RB0/INT0/FLT0 2 47 RB1/INT1 RG0/ECCP3/P3A RG1/TX2/CK2/AN19/C3OUT 3 4 46 45 RB3/INT3/CTED2/ECCP2(1)/PA2 RB2/INT2/CTED1 RG2/RX2
PIC18F87K22 FAMILY Pin Diagrams – PIC18F8XK22 RH1/AN22/A17 RH0/AN23/A16 RE2/P2B/CCP10(2)/CS/AD10 RE3/P3C/CCP9(2,3)/REF0/AD11 RE4/P3B/CCP8(3)/AD12 RE5/P1C/CCP7(3)/AD13 RE6/P1B/CCP6(3)/AD14 RE7/ECCP2/P2A/AD15 RD0/PSP0/CTPLS/AD0 VDD VSS RD1/T5CKI/T7G/PSP1/AD1 RD2/PSP2/AD2 RD3/PSP3/AD3 RD4/SDO2/PSP4/AD4 RD5/SDI2/SDA2/PSP5/AD5 RD6/SCK2/SCL2/PSP6/AD6 RD7/SS2/PSP7/AD7 RJ0/ALE RJ1/OE 80-Pin TQFP 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 RH2/AN21/A18 RH3/AN20/A19 RE1/P2C/WR/AD9 RE0/P2D/RD/AD8 R
PIC18F87K22 FAMILY Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 Guidelines for Getting Started with PIC18FXXKXX Microcontrollers ......................................................................................... 37 3.0 Oscillator Configurations ..........................................................................................
PIC18F87K22 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.
PIC18F87K22 FAMILY 1.0 DEVICE OVERVIEW This document contains device-specific information for the following devices: • PIC18F65K22 • PIC18F66K22 • PIC18F67K22 • PIC18F85K22 • PIC18F86K22 • PIC18F87K22 This family combines the traditional advantages of all PIC18 microcontrollers – namely, high computational performance and a rich feature set – with an extremely competitive price point.
PIC18F87K22 FAMILY 1.1.6 EASY MIGRATION All devices share the same rich set of peripherals except that the devices with 32 Kbytes of program memory (PIC18F65K22 and PIC18F85K22) have two less CCPs and three less timers. This provides a smooth migration path within the device family as applications evolve and grow. The consistent pinout scheme, used throughout the entire family, also aids in migrating to the next larger device.
PIC18F87K22 FAMILY 1.3 Details on Individual Family Members Devices in the PIC18F87K22 family are available in 64-pin and 80-pin packages. Block diagrams for the two groups are shown in Figure 1-1 and Figure 1-2.
PIC18F87K22 FAMILY TABLE 1-1: DEVICE FEATURES FOR THE PIC18F6XK22 (64-PIN DEVICES) Features PIC18F65K22 Operating Frequency Program Memory (Bytes) Program Memory (Instructions) PIC18F66K22 PIC18F67K22 DC – 64 MHz 32K 64K 128K 16,384 32,768 65,536 Data Memory (Bytes) 2K 4K 4K Interrupt Sources 42 48 I/O Ports Ports A, B, C, D, E, F, G Parallel Communications Timers Parallel Slave Port (PSP) 8 11 Comparators 3 CTMU Yes RTCC Yes Capture/Compare/PWM (CCP) Modules 5 7 Enhanced CC
PIC18F87K22 FAMILY FIGURE 1-1: PIC18F6XK22 (64-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> 20 Address Latch PCU PCH PCL Program Counter 12 Data Address<12> 31-Level Stack 4 BSR Address Latch Program Memory STKPTR PORTB RB0:RB7(1) 4 Access Bank 12 FSR0 FSR1 FSR2 Data Latch 8 RA0:RA7(1,2) Data Memory (2/4 Kbytes) PCLATU PCLATH 21 PORTA Data Latch 8 8 inc/dec logic 12 PORTC RC0:RC7(1) inc/dec logic Table Latch Address Decode ROM Latch Instruction Bus <16> PORTD RD0:RD7(1) IR
PIC18F87K22 FAMILY FIGURE 1-2: PIC18F8XK22 (80-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> 20 Address Latch PCU PCH PCL Program Counter 31-Level Stack 4 BSR System Bus Interface STKPTR 12 RB0:RB7(1) 4 Access Bank FSR0 FSR1 FSR2 Data Latch 8 PORTB 12 Data Address<12> Address Latch Program Memory RA0:RA7(1,2) Data Memory (2/4 Kbytes) PCLATU PCLATH 21 PORTA Data Latch 8 8 inc/dec logic PORTC RC0:RC7(1) 12 inc/dec logic Table Latch PORTD RD0:RD7(1) Address Decode ROM Latch
PIC18F87K22 FAMILY TABLE 1-3: PIC18F6XK22 PINOUT I/O DESCRIPTIONS Pin Name Pin Number Pin Buffer QFN/TQFP Type Type 7 MCLR/RG5 MCLR RG5 Master Clear (input) or programming voltage (input). I I ST ST I I CMOS CMOS I/O TTL O — CLKO O — RA6 I/O TTL OSC1/CLKI/RA7 OSC1 CLKI 39 RA7 OSC2/CLKO/RA6 OSC2 Description 40 This pin is an active-low Reset to the device. General purpose, input only pin. Oscillator crystal or external clock input. Oscillator crystal input.
PIC18F87K22 FAMILY TABLE 1-3: PIC18F6XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Buffer QFN/TQFP Type Type Description PORTA is a bidirectional I/O port. RA0/AN0/ULPWU RA0 AN0 ULPWU 24 RA1/AN1 RA1 AN1 23 RA2/AN2/VREFRA2 AN2 VREF- 22 RA3/AN3/VREF+ RA3 AN3 VREF+ 21 RA4/T0CKI RA4 T0CKI 28 RA5/AN4/T1CKI/T3G/ HLVDIN RA5 AN4 T1CKI T3G HLVDIN 27 I/O I I TTL Analog Analog Digital I/O. Analog Input 0. Ultra Low-Power Wake-up input. I/O I TTL Analog Digital I/O.
PIC18F87K22 FAMILY TABLE 1-3: PIC18F6XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Buffer QFN/TQFP Type Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
PIC18F87K22 FAMILY TABLE 1-3: PIC18F6XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Buffer QFN/TQFP Type Type Description PORTC is a bidirectional I/O port. RC0/SOSCO/SCLKI RC0 SOSCO SCLKI 30 RC1/SOSCI/ECCP2/P2A RC1 SOSCI ECCP2(1) P2A 29 RC2/ECCP1/P1A RC2 ECCP1 P1A 33 RC3/SCK1/SCL1 RC3 SCK1 SCL1(4) 34 RC4/SDI1/SDA1 RC4 SDI1 SDA1(4) 35 RC5/SDO1 RC5 SDO1 36 RC6/TX1/CK1 RC6 TX1 CK1 31 RC7/RX1/DT1 RC7 RX1 DT1 32 I/O O I ST — ST I/O I I/O O ST CMOS ST — Digital I/O.
PIC18F87K22 FAMILY TABLE 1-3: PIC18F6XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Buffer QFN/TQFP Type Type Description PORTD is a bidirectional I/O port. RD0/PSP0/CTPLS RD0 PSP0 CTPLS 58 RD1/PSP1/T5CKI/T7G RD1 PSP1 T5CKI T7G 55 RD2/PSP2 RD2 PSP2 54 RD3/PSP3 RD3 PSP3 53 RD4/PSP4/SDO2 RD4 PSP4 SDO2 52 RD5/PSP5/SDI2/SDA2 RD5 PSP5 SDI2 SDA2 51 RD6/PSP6/SCK2/SCL2 RD6 PSP6 SCK2 SCL2(4) 50 RD7/PSP7/SS2 RD7 PSP7 SS2 49 I/O I/O O ST TTL — Digital I/O.
PIC18F87K22 FAMILY TABLE 1-3: PIC18F6XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Buffer QFN/TQFP Type Type Description PORTE is a bidirectional I/O port. RE0/RD/P2D RE0 RD P2D 2 RE1/WR/P2C RE1 WR P2C 1 RE2/CS/P2B/CCP10 RE2 CS P2B CCP10(3) 64 RE3/P3C/CCP9/REFO RE3 P3C CCP9(3,4) REFO 63 RE4/P3B/CCP8 RE4 P3B CCP8(4) 62 RE5/P1C/CCP7 RE5 P1C CCP7(4) 61 RE6/P1B/CCP6 RE6 P1B CCP6(4 60 RE7/ECCP2/P2A RE7 ECCP2(2) P2A 59 I/O I O ST TTL — Digital I/O.
PIC18F87K22 FAMILY TABLE 1-3: PIC18F6XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Buffer QFN/TQFP Type Type Description PORTF is a bidirectional I/O port. RF1/AN6/C2OUT/CTDIN RF1 AN6 C2OUT CTDIN 17 RF2/AN7/C1OUT RF2 AN7 C1OUT 16 RF3/AN8/C2INB/CTMUI RF3 AN8 C2INB CTMUI 15 RF4/AN9/C2INA RF4 AN9 C2INA 14 RF5/AN10/CVREF/C1INB RF5 AN10 CVREF C1INB 13 RF6/AN11/C1INA RF6 AN11 C1INA 12 RF7/AN5/SS1 RF7 AN5 SS1 11 I/O I O I ST Analog — ST Digital I/O. Analog Input 6.
PIC18F87K22 FAMILY TABLE 1-3: PIC18F6XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Buffer QFN/TQFP Type Type Description PORTG is a bidirectional I/O port.
PIC18F87K22 FAMILY TABLE 1-3: PIC18F6XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Buffer QFN/TQFP Type Type Description VSS 9, 25, 41, 56 P — Ground reference for logic and I/O pins. VDD 26, 38, 57 P — Positive supply for logic and I/O pins. AVSS 20 P — Ground reference for analog modules. AVDD 19 P — Positive supply for analog modules. ENVREG 18 I ST VDDCORE/VCAP VDDCORE VCAP 10 Enable for on-chip voltage regulator.
PIC18F87K22 FAMILY TABLE 1-4: PIC18F8XK22 PINOUT I/O DESCRIPTIONS Pin Number Pin Name TQFP Pin Buffer Type Type 9 MCLR/RG5 RG5 MCLR Master Clear (input) or programming voltage (input). I I ST ST I I CMOS CMOS I/O TTL O — CLKO O — RA6 I/O TTL OSC1/CLKI/RA7 OSC1 CLKI 49 RA7 OSC2/CLKO/RA6 OSC2 Description 50 This pin is an active-low Reset to the device. General purpose, input only pin. Oscillator crystal or external clock input. Oscillator crystal input. External clock source input.
PIC18F87K22 FAMILY TABLE 1-4: PIC18F8XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Buffer Type Type Description PORTA is a bidirectional I/O port. RA0/AN0/ULPWU RA0 AN0 ULPWU 30 RA1/AN1 RA1 AN1 29 RA2/AN2/VREFRA2 AN2 VREF- 28 RA3/AN3/VREF+ RA3 AN3 VREF+ 27 RA4/T0CKI RA4 T0CKI 34 RA5/AN4/T1CKI/ T3G/HLVDIN RA5 AN4 T1CKI T3G HLVDIN 33 I/O I I TTL Analog Analog Digital I/O. Analog Input 0. Ultra Low-Power Wake-up input. I/O I TTL Analog Digital I/O. Analog Input 1.
PIC18F87K22 FAMILY TABLE 1-4: PIC18F8XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Buffer Type Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
PIC18F87K22 FAMILY TABLE 1-4: PIC18F8XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Buffer Type Type Description PORTC is a bidirectional I/O port. RC0/SOSCO/SCKLI RC0 SOSCO SCKLI 36 RC1/SOSCI/ECCP2/P2A RC1 SOSCI ECCP2(1) P2A 35 RC2/ECCP1/P1A RC2 ECCP1 P1A 43 RC3/SCK1/SCL1 RC3 SCK1 SCL1 44 RC4/SDI1/SDA1 RC4 SDI1 SDA1 45 RC5/SDO1 RC5 SDO1 46 RC6/TX1/CK1 RC6 TX1 CK1 37 RC7/RX1/DT1 RC7 RX1 DT1 38 I/O O I ST — ST I/O I I/O O ST CMOS ST — Digital I/O.
PIC18F87K22 FAMILY TABLE 1-4: PIC18F8XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Buffer Type Type Description PORTD is a bidirectional I/O port.
PIC18F87K22 FAMILY TABLE 1-4: PIC18F8XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RD6/SCK2/SCL2/PSP6/ AD6 RD6 SCK2 SCL2 PSP6(4) AD6 64 RD7/SS2/PSP7/AD7 RD7 SS2 PSP7(4) AD7 63 Pin Buffer Type Type Description I/O I/O I/O I/O I/O ST ST I2C TTL TTL Digital I/O. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I2C™ mode. Parallel Slave Port data. External Memory Address/Data 6. I/O I I/O I/O ST TTL TTL TTL Digital I/O.
PIC18F87K22 FAMILY TABLE 1-4: PIC18F8XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Buffer Type Type Description PORTE is a bidirectional I/O port. RE0/P2D/RD/AD8 RE0 P2D RD(4) AD8 4 RE1/P2C/WR/AD9 RE1 P2C WR(4) AD9 3 RE2/P2B/CCP10/CS/ AD10 RE2 P2B CCP10(3) CS(4) AD10 78 RE3/P3C/CCP9/REFO AD11 RE3 P3C CCP9(3,5) REFO AD11 77 RE4/P3B/CCP8/AD12 RE4 P3B CCP8(5) AD12 76 RE5/P1C/CCP7/AD13 RE5 P1C CCP7(5) AD13 75 I/O O I I/O ST — TTL TTL Digital I/O. ECCP2 PWM Output D.
PIC18F87K22 FAMILY TABLE 1-4: PIC18F8XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RE6/P1B/CCP6/AD14 RE6 P1B CCP6(5) AD14 74 RE7/ECCP2/P2A/AD15 RE7 ECCP2(2) P2A AD15 73 Pin Buffer Type Type Description I/O O I/O I/O ST — ST ST Digital I/O. ECCP1 PWM Output B. Capture 6 input/Compare 6 output/PWM6 output. External Memory Address/Data 14. I/O I/O O I/O ST ST — ST Digital I/O. Capture 2 input/Compare 2 output/PWM2 output. ECCP2 PWM Output A. External Memory Address/Data 15.
PIC18F87K22 FAMILY TABLE 1-4: PIC18F8XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Buffer Type Type Description PORTF is a bidirectional I/O port. RF1/AN6/C2OUT/CTDIN RF1 AN6 C2OUT CTDIN 23 RF2/AN7/C1OUT RF2 AN7 C1OUT 18 RF3/AN8/C2INB/CTMUI RF3 AN8 C2INB CTMUI 17 RF4/AN9/C2INA RF4 AN9 C2INA 16 RF5/AN10/C1INB RF5 AN10 C1INB 15 RF6/AN11/C1INA RF6 AN11 C1INA 14 RF7/AN5/SS1 RF7 AN5 SS1 13 I/O I O I ST Analog — ST Digital I/O. Analog Input 6. Comparator 2 output.
PIC18F87K22 FAMILY TABLE 1-4: PIC18F8XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Buffer Type Type Description PORTG is a bidirectional I/O port.
PIC18F87K22 FAMILY TABLE 1-4: PIC18F8XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Buffer Type Type Description PORTH is a bidirectional I/O port. RH0/AN23/A16 RH0 AN23 A16 79 RH1/AN22/A17 RH1 AN22 A17 80 RH2/AN21/A18 RH2 AN21 A18 1 RH3/AN20/A19 RH3 AN20 A19 2 RH4/CCP9/P3C/AN12/ C2INC RH4 CCP9(3,5) P3C AN12 C2INC 22 RH5/CCP8/P3B/AN13/ C2IND RH5 CCP8(5) P3B AN13 C2IND 21 RH6/CCP7/P1C/AN14/ C1INC RH6 CCP7(5) P1C AN14 C1INC 20 I/O I I/O ST Analog TTL Digital I/O.
PIC18F87K22 FAMILY TABLE 1-4: PIC18F8XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RH7/CCP6/P1B/AN15 RH7 CCP6(5) P1B AN15 Pin Buffer Type Type Description 19 I/O I/O O I ST ST — Analog Digital I/O. Capture 6 input/Compare 6 output/PWM6 output. ECCP1 PWM Output B. Analog Input 15.
PIC18F87K22 FAMILY TABLE 1-4: PIC18F8XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Buffer Type Type Description PORTJ is a bidirectional I/O port. RJ0/ALE RJ0 ALE 62 RJ1/OE RJ1 OE 61 RJ2/WRL RJ2 WRL 60 RJ3/WRH RJ3 WRH 59 RJ4/BA0 RJ4 BA0 39 RJ5/CE RJ5 CE 40 RJ6/LB RJ6 LB 41 RJ7/UB RJ7 UB 42 I/O O ST — Digital I/O. External memory address latch enable. I/O O ST — Digital I/O. External memory output enable. I/O O ST — Digital I/O.
PIC18F87K22 FAMILY 2.0 GUIDELINES FOR GETTING STARTED WITH PIC18FXXKXX MICROCONTROLLERS FIGURE 2-1: RECOMMENDED MINIMUM CONNECTIONS C2(2) • All VDD and VSS pins (see Section 2.2 “Power Supply Pins”) • All AVDD and AVSS pins, regardless of whether or not the analog device features are used (see Section 2.2 “Power Supply Pins”) • MCLR pin (see Section 2.3 “Master Clear (MCLR) Pin”) • ENVREG (if implemented) and VCAP/VDDCORE pins (see Section 2.
PIC18F87K22 FAMILY 2.2 2.2.1 Power Supply Pins DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS, is required. Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device, with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are recommended.
PIC18F87K22 FAMILY 2.4 Some PIC18FXXKXX families, or some devices within a family, do not provide the option of enabling or disabling the on-chip voltage regulator: Voltage Regulator Pins (ENVREG and VCAP/VDDCORE) The on-chip voltage regulator enable pin, ENVREG, must always be connected directly to either a supply voltage or to ground. Tying ENVREG to VDD enables the regulator, while tying it to ground disables the regulator. Refer to Section 28.
PIC18F87K22 FAMILY CONSIDERATIONS FOR CERAMIC CAPACITORS In recent years, large value, low-voltage, surface-mount ceramic capacitors have become very cost effective in sizes up to a few tens of microfarad. The low-ESR, small physical size and other properties make ceramic capacitors very attractive in many types of applications. Ceramic capacitors are suitable for use with the internal voltage regulator of this microcontroller.
PIC18F87K22 FAMILY 2.6 External Oscillator Pins FIGURE 2-5: Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 3.0 “Oscillator Configurations” for details). The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0.5 inch (12 mm) between the circuit components and the pins.
PIC18F87K22 FAMILY NOTES: DS39960D-page 42 2009-2011 Microchip Technology Inc.
PIC18F87K22 FAMILY 3.0 OSCILLATOR CONFIGURATIONS 3.
PIC18F87K22 FAMILY TABLE 3-1: HS, EC, XT, LP AND RC MODES: RANGES AND SETTINGS Mode Frequency Range EC1 (low power) FOSC<3:0> Setting 1101 DC-160 kHz (EC1 & EC1IO) EC2 (medium power) 1100 160 kHz-16 MHz 1011 16 MHz-64 MHz 0101 HS1 (medium power) 4 MHz-16 MHz 0011 HS2 (high power) 16 MHz-25 MHz 0010 XT 100 kHz-4 MHz 0001 LP 31.
PIC18F87K22 FAMILY 3.2 Control Registers The OSCCON register (Register 3-1) controls the main aspects of the device clock’s operation. It selects the oscillator type to be used, which of the power-managed modes to invoke and the output frequency of the INTOSC source. It also provides status on the oscillators. OSCCON: OSCILLATOR CONTROL REGISTER(1) REGISTER 3-1: R/W-0 R/W-1 IDLEN The OSCTUNE register (Register 3-3) controls the tuning and operation of the internal oscillator block.
PIC18F87K22 FAMILY REGISTER 3-1: OSCCON: OSCILLATOR CONTROL REGISTER(1) (CONTINUED) bit 2 HFIOFS: INTOSC Frequency Stable bit 1 = HF-INTOSC oscillator frequency is stable 0 = HF-INTOSC oscillator frequency is not stable bit 1-0 SCS<1:0>: System Clock Select bits(4) 1x = Internal oscillator block (LF-INTOSC, MF-INTOSC or HF-INTOSC) 01 = SOSC oscillator 00 = Default primary oscillator (OSC1/OSC2 or HF-INTOSC with or without PLL; defined by the FOSC<3:0> Configuration bits, CONFIG1H<3:0>.
PIC18F87K22 FAMILY REGISTER 3-3: OSCTUNE: OSCILLATOR TUNING REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTSRC PLLEN TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit 1 = 31.
PIC18F87K22 FAMILY 3.3 Clock Sources and Oscillator Switching Essentially, PIC18F87K22 family devices have these independent clock sources: • Primary oscillators • Secondary oscillators • Internal oscillator The primary oscillators can be thought of as the main device oscillators. These are any external oscillators connected to the OSC1 and OSC2 pins, and include the External Crystal and Resonator modes and the External Clock modes.
PIC18F87K22 FAMILY The use of the flag and control bits in the OSCCON register is discussed in more detail in Section 4.0 “Power-Managed Modes”. Note 1: The Timer1/3/5/7 oscillator must be enabled to select the secondary clock source. The Timerx oscillator is enabled by setting the SOSCEN bit in the Timerx Control register (TxCON<3>). If the Timerx oscillator is not enabled, then any attempt to select a secondary clock source when executing a SLEEP instruction will be ignored.
PIC18F87K22 FAMILY 3.5 TABLE 3-3: External Oscillator Modes 3.5.1 CRYSTAL OSCILLATOR/CERAMIC RESONATORS (HS MODES) In HS or HSPLL Oscillator modes, a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation. Figure 3-4 shows the pin connections. The oscillator design requires the use of a crystal rated for parallel resonant operation. Note: Use of a crystal rated for series resonant operation may give a frequency out of the crystal manufacturer’s specifications.
PIC18F87K22 FAMILY 3.5.2 EXTERNAL CLOCK INPUT (EC MODES) The EC and ECPLL Oscillator modes require an external clock source to be connected to the OSC1 pin. There is no oscillator start-up time required after a Power-on Reset or after an exit from Sleep mode. In the EC Oscillator mode, the oscillator frequency, divided by 4, is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. Figure 3-5 shows the pin connections for the EC Oscillator mode.
PIC18F87K22 FAMILY 3.6 Internal Oscillator Block The PIC18F87K22 family of devices includes an internal oscillator block which generates two different clock signals. Either clock can be used as the microcontroller’s clock source, which may eliminate the need for an external oscillator circuit on the OSC1 and/or OSC2 pins. The internal oscillator consists of three blocks, depending on the frequency of operation. They are HF-INTOSC, MF-INTOSC and LF-INTRC.
PIC18F87K22 FAMILY 3.6.3 INTERNAL OSCILLATOR OUTPUT FREQUENCY AND TUNING The internal oscillator block is calibrated at the factory to produce an INTOSC output frequency of 16 MHz. It can be adjusted in the user’s application by writing to TUN<5:0> (OSCTUNE<5:0>) in the OSCTUNE register (Register 3-3). When the OSCTUNE register is modified, the INTOSC (HF-INTOSC and MF-INTOSC) frequency will begin shifting to the new frequency. The oscillator will require some time to stabilize.
PIC18F87K22 FAMILY REGISTER 3-4: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ROON — ROSSLP ROSEL(1) RODIV3 RODIV2 RODIV1 RODIV0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ROON: Reference Oscillator Output Enable bit 1 = Reference oscillator output is available on REFO pin 0 = Reference oscillator output is
PIC18F87K22 FAMILY 3.8 Effects of Power-Managed Modes on the Various Clock Sources When PRI_IDLE mode is selected, the designated primary oscillator continues to run without interruption. For all other power-managed modes, the oscillator using the OSC1 pin is disabled. The OSC1 pin (and OSC2 pin if used by the oscillator) will stop oscillating. In secondary clock modes (SEC_RUN and SEC_IDLE), the SOSC oscillator is operating and providing the device clock.
PIC18F87K22 FAMILY NOTES: DS39960D-page 56 2009-2011 Microchip Technology Inc.
PIC18F87K22 FAMILY 4.0 POWER-MANAGED MODES The PIC18F87K22 family of devices offers a total of seven operating modes for more efficient power management. These modes provide a variety of options for selective power conservation in applications where resources may be limited (such as battery-powered devices). There are three categories of power-managed mode: • Run modes • Idle modes • Sleep mode There is an Ultra Low-Power Wake-up (ULPWU) for waking from the Sleep mode.
PIC18F87K22 FAMILY 4.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. The HF-INTOSC and MF-INTOSC are termed as INTOSC in this chapter. Three bits indicate the current clock source and its status, as shown in Table 4-2.
PIC18F87K22 FAMILY FIGURE 4-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 1 SOSCI 2 3 n-1 Q3 Q4 Q1 Q2 Q3 n Clock Transition(1) OSC1 CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 Note 1: Clock transition typically occurs within 2-4 TOSC.
PIC18F87K22 FAMILY 4.2.3 RC_RUN MODE In RC_RUN mode, the CPU and peripherals are clocked from the internal oscillator block using the INTOSC multiplexer. In this mode, the primary clock is shut down. When using the LF-INTOSC source, this mode provides the best power conservation of all the Run modes, while still executing code. It works well for user applications which are not highly timing-sensitive or do not require high-speed clocks at all times.
PIC18F87K22 FAMILY Clocks to the device continue while the INTOSC source stabilizes after an interval of TIOBST (Parameter 39, Table 31-13). On transitions from RC_RUN mode to PRI_RUN mode, the device continues to be clocked from the INTOSC multiplexer while the primary clock is started. When the primary clock becomes ready, a clock switch to the primary clock occurs (see Figure 4-4).
PIC18F87K22 FAMILY 4.3 Sleep Mode 4.4 The power-managed Sleep mode in the PIC18F87K22 family of devices is identical to the legacy Sleep mode offered in all other PIC devices. It is entered by clearing the IDLEN bit (the default state on device Reset) and executing the SLEEP instruction. This shuts down the selected oscillator (Figure 4-5). All clock source status bits are cleared.
PIC18F87K22 FAMILY 4.4.1 PRI_IDLE MODE 4.4.2 This mode is unique among the three low-power Idle modes, in that it does not disable the primary device clock. For timing-sensitive applications, this allows for the fastest resumption of device operation with its more accurate, primary clock source, since the clock source does not have to “warm-up” or transition from another oscillator. PRI_IDLE mode is entered from PRI_RUN mode by setting the IDLEN bit and executing a SLEEP instruction.
PIC18F87K22 FAMILY 4.4.3 RC_IDLE MODE In RC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the internal oscillator block using the INTOSC multiplexer. This mode provides controllable power conservation during Idle periods. From RC_RUN, this mode is entered by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, first set IDLEN, then set the SCS1 bit and execute SLEEP.
PIC18F87K22 FAMILY REGISTER 4-1: R/W-0 (1) CCP10MD PMD3: PERIPHERAL MODULE DISABLE REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CCP9MD(1) CCP8MD CCP7MD CCP6MD CCP5MD CCP4MD TMR12MD(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CCP10MD: PMD CCP10 Enable/Disable bit(1) 1 = Peripheral Module Disable (PMD) is enabled for CCP10, disabling all of its cloc
PIC18F87K22 FAMILY REGISTER 4-2: PMD2: PERIPHERAL MODULE DISABLE REGISTER 2 R/W-0 (1) TMR10MD R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TMR8MD TMR7MD(1) TMR6MD TMR5MD CMP3MD CMP2MD CMP1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TMR10MD: TMR10MD Disable bit(1) 1 = Peripheral Module Disable (PMD) is enabled and all TMR10MD clock sources are disabled 0 =
PIC18F87K22 FAMILY REGISTER 4-3: PMD1: PERIPHERAL MODULE DISABLE REGISTER 1 R/W-0 R/W-0 PSPMD CTMUMD R/W-0 (1) RTCCMD R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TMR4MD TMR3MD TMR2MD TMR1MD EMBMD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PSPMD: Peripheral Module Disable (PMD) PSP Enable/Disable bit 1 = PMD is enabled for PSP, disabling all of its clock sources 0 = PMD is disabled for PSP
PIC18F87K22 FAMILY REGISTER 4-4: PMD0: PERIPHERAL MODULE DISABLE REGISTER 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CCP3MD CCP2MD CCP1MD UART2MD UART1MD SSP2MD SSP1MD ADCMD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CCP3MD: PMD ECCP3 Enable/Disable bit 1 = Peripheral Module Disable (PMD) is enabled for ECCP3, disabling all of its clock sources 0 =
PIC18F87K22 FAMILY 4.6 Exiting Idle and Sleep Modes An exit from Sleep mode or any of the Idle modes is triggered by an interrupt, a Reset or a WDT time-out. This section discusses the triggers that cause exits from power-managed modes. The clocking subsystem actions are discussed in each of the power-managed modes (see Section 4.2 “Run Modes”, Section 4.3 “Sleep Mode” and Section 4.4 “Idle Modes”). 4.6.
PIC18F87K22 FAMILY 4.7 Ultra Low-Power Wake-up The Ultra Low-Power Wake-up (ULPWU) on pin, RA0, allows a slow falling voltage to generate an interrupt without excess current consumption. To use this feature: 1. 2. 3. 4. 5. A series resistor, between RA0 and the external capacitor, provides overcurrent protection for the RA0/AN0/ ULPWU pin and enables software calibration of the time-out (see Figure 4-9).
PIC18F87K22 FAMILY TABLE 4-4: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE (BY CLOCK SOURCES) Power-Managed Mode Clock Source(5) Exit Delay Clock Ready Status Bits LP, XT, HS HSPLL PRI_IDLE mode EC, RC HF-INTOSC(2) OSTS TCSD(1) MF-INTOSC(2) LF-INTOSC SEC_IDLE mode SOSC None TCSD(1) SOSCRUN TCSD(1) MFIOFS HF-INTOSC(2) RC_IDLE mode MF-INTOSC(2) HFIOFS LF-INTOSC Sleep mode TOST(3) HSPLL TOST + trc(3) EC, RC TCSD(1) HF-INTOSC(2) LF-INTOSC Note 1: 2: 3: 4: 5: None L
PIC18F87K22 FAMILY NOTES: DS39960D-page 72 2009-2011 Microchip Technology Inc.
PIC18F87K22 FAMILY 5.0 RESET 5.1 The PIC18F87K22 family of devices differentiates between various kinds of Reset: a) b) c) d) e) f) g) h) i) Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during power-managed modes Watchdog Timer (WDT) Reset (during execution) Configuration Mismatch (CM) Reset Brown-out Reset (BOR) RESET Instruction Stack Full Reset Stack Underflow Reset RCON Register Device Reset events are tracked through the RCON register (Register 5-1).
PIC18F87K22 FAMILY REGISTER 5-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-1 R/W-1 R/W-1 R-1 R-1 R/W-0 R/W-0 IPEN SBOREN CM RI TO PD POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 SBOREN: BOR Softwa
PIC18F87K22 FAMILY 5.2 Master Clear (MCLR) The MCLR pin provides a method for triggering a hard external Reset of the device. A Reset is generated by holding the pin low. PIC18 extended microcontroller devices have a noise filter in the MCLR Reset path which detects and ignores small pulses. The MCLR pin is not driven low by any internal Resets, including the WDT. 5.3 Power-on Reset (POR) A Power-on Reset condition is generated on-chip whenever VDD rises above a certain threshold.
PIC18F87K22 FAMILY 5.5 Configuration Mismatch (CM) 5.6 Power-up Timer (PWRT) The Configuration Mismatch (CM) Reset is designed to detect, and attempt to recover from, random, memory corrupting events. These include Electrostatic Discharge (ESD) events that can cause widespread, single bit changes throughout the device and result in catastrophic failure. PIC18F87K22 family devices incorporate an on-chip Power-up Timer (PWRT) to help regulate the Power-on Reset process.
PIC18F87K22 FAMILY FIGURE 5-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 FIGURE 5-5: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET FIGURE 5-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) 3.3V VDD 0V 1V MCLR INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET 2009-2011 Microchip Technology Inc.
PIC18F87K22 FAMILY 5.7 different Reset situations, as indicated in Table 5-1. These bits are used in software to determine the nature of the Reset. Reset State of Registers Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred. Table 5-2 describes the Reset states for all of the Special Function Registers.
PIC18F87K22 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets, CM Resets TOSU PIC18F6XK22 PIC18F8XK22 ---0 0000 ---0 0000 ---0 uuuu(1) TOSH PIC18F6XK22 PIC18F8XK22 0000 0000 0000 0000 uuuu uuuu(1) TOSL PIC18F6XK22 PIC18F8XK22 0000 0000 0000 0000 uuuu uuuu(1) STKPTR PIC18F6XK22 PIC18F8XK22 00-0 0000 uu-0 0000 uu-u uuuu(1) PCLATU PIC18F6XK22 PIC18F8XK22 ---0 0000 -
PIC18F87K22 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets, CM Resets INDF2 PIC18F6XK22 PIC18F8XK22 N/A N/A POSTINC2 PIC18F6XK22 PIC18F8XK22 N/A N/A N/A POSTDEC2 PIC18F6XK22 PIC18F8XK22 N/A N/A N/A PREINC2 PIC18F6XK22 PIC18F8XK22 N/A N/A N/A PLUSW2 PIC18F6XK22 PIC18F8XK22 N/A N/A N/A FSR2H PIC18F6XK22 PIC18F8XK22 ---- xxxx ----uuuu ---- uuuu
PIC18F87K22 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets, CM Resets ECCP1AS PIC18F6XK22 PIC18F8XK22 0000 0000 0000 0000 uuuu uuuu ECCP1DEL PIC18F6XK22 PIC18F8XK22 0000 0000 0000 0000 uuuu uuuu CCPR1H PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu CCPR1L PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON PIC18F6XK22 PIC18F8XK22 00
PIC18F87K22 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets, CM Resets IPR3 PIC18F6XK22 PIC18F8XK22 1-11 1111 1-11 1111 u-uu uuuu PIR3 PIC18F6XK22 PIC18F8XK22 0-00 0000 0-00 0000 u-uu uuuu PIE3 PIC18F6XK22 PIC18F8XK22 0-00 0000 0-00 0000 u-uu uuuu IPR2 PIC18F6XK22 PIC18F8XK22 1-11 1111 1-11 1111 u-uu uuuu PIR2 PIC18F6XK22 PIC18F8XK22 0-10 0000 0-10
PIC18F87K22 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets, CM Resets PORTC PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu PORTB PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu PORTA PIC18F6XK22 PIC18F8XK22 xx0x 0000 uu0u 0000 uuuu uuuu EECON1 PIC18F6XK22 PIC18F8XK22 xx-0 x000 uu-0 u000 uu-u uuuu EECON2 PIC18F6XK22 PIC18F8XK22 ---- ----
PIC18F87K22 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets, CM Resets Wake-up via WDT or Interrupt RTCCFG PIC18F6XK22 PIC18F8XK22 0-00 0000 u-uu uuuu u-uu uuuu RTCCAL PIC18F6XK22 PIC18F8XK22 0000 0000 uuuu uuuu uuuu uuuu RTCVALH PIC18F6XK22 PIC18F8XK22 xxxx xxxx uuuu uuuu uuuu uuuu RTCVALL PIC18F6XK22 PIC18F8XK22 0000 0000 uuuu uuuu uuuu uuu
PIC18F87K22 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets, CM Resets CCP10CON PIC18F66K22 PIC18F86K22 PIC18F67K22 PIC18F87K22 --00 0000 --00 0000 --uu uuuu TMR7H PIC18F66K22 PIC18F86K22 PIC18F67K22 PIC18F87K22 xxxx xxxx uuuu uuuu uuuu uuuu TMR7L PIC18F66K22 PIC18F86K22 PIC18F67K22 PIC18F87K22 xxxx xxxx uuuu uuuu uuuu uuuu T7CON PIC18F66K22 PIC18F86K22 PI
PIC18F87K22 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets, CM Resets PIC18F66K22 PIC18F86K22 PIC18F67K22 PIC18F87K22 0000 0000 uuuu uuuu uuuu uuuu ODCON2 PIC18F65K22 PIC18F85K22 --00 0000 --uu uuuu --uu uuuu ODCON3 PIC18F6XK22 PIC18F8XK22 00-- ---0 uu-- ---u uu-- ---u MEMCON PIC18F6XK22 PIC18F8XK22 0-00 --00 0-00 --00 u-uu --uu ANCON0 PIC18F6XK22 PI
PIC18F87K22 FAMILY 6.0 MEMORY ORGANIZATION PIC18F87K22 family devices have these types of memory: • Program Memory • Data RAM • Data EEPROM As Harvard architecture devices, the data and program memories use separate busses. This enables concurrent access of the two memory spaces. FIGURE 6-1: The data EEPROM, for practical purposes, can be regarded as a peripheral device because it is addressed and accessed through a set of control registers.
PIC18F87K22 FAMILY 6.1 Program Memory Organization PIC18 microcontrollers implement a 21-bit Program Counter that is capable of addressing a 2-Mbyte program memory space. Accessing a location between the upper boundary of the physically implemented memory and the 2-Mbyte address will return all ‘0’s (a NOP instruction). The entire PIC18F87K22 family offers a range of on-chip Flash program memory sizes, from 32 Kbytes (up to 16,384 single-word instructions) to 128 Kbytes (65,536 single-word instructions).
PIC18F87K22 FAMILY 6.1.2 PROGRAM COUNTER The Program Counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21 bits wide and contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC<15:8> bits and is not directly readable or writable. Updates to the PCH register are performed through the PCLATH register. The upper byte is called PCU.
PIC18F87K22 FAMILY 6.1.3.2 Return Stack Pointer (STKPTR) The STKPTR register (Register 6-1) contains the Stack Pointer value, the STKFUL (Stack Full) status bit and the STKUNF (Stack Underflow) status bits. The value of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the stack and decrements after values are popped off the stack. On Reset, the Stack Pointer value will be zero.
PIC18F87K22 FAMILY 6.1.3.4 Stack Full and Underflow Resets Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit (CONFIG4L<0>). When STVREN is set, a full or underflow condition will set the appropriate STKFUL or STKUNF bit and then cause a device Reset. When STVREN is cleared, a full or underflow condition will set the appropriate STKFUL or STKUNF bit, but not cause a device Reset.
PIC18F87K22 FAMILY 6.2 6.2.2 PIC18 Instruction Cycle 6.2.1 An “Instruction Cycle” consists of four Q cycles, Q1 through Q4. The instruction fetch and execute are pipelined in such a manner that a fetch takes one instruction cycle, while the decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction (such as GOTO) causes the Program Counter to change, two cycles are required to complete the instruction.
PIC18F87K22 FAMILY 6.2.3 INSTRUCTIONS IN PROGRAM MEMORY The program memory is addressed in bytes. Instructions are stored as two or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSB = 0). To maintain alignment with instruction boundaries, the PC increments in steps of two and the LSB will always read ‘0’ (see Section 6.1.2 “Program Counter”).
PIC18F87K22 FAMILY 6.3 Note: Data Memory Organization The operation of some aspects of data memory are changed when the PIC18 extended instruction set is enabled. See Section 6.6 “Data Memory and the Extended Instruction Set” for more information. The data memory in PIC18 devices is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4,096 bytes of data memory. The memory space is divided into as many as 16 banks that contain 256 bytes each.
PIC18F87K22 FAMILY FIGURE 6-6: DATA MEMORY MAP FOR PIC18FX5K22 AND PIC18FX7K22 DEVICES BSR<3:0> Data Memory Map 00h = 0000 = 0001 = 0010 = 0011 = 0100 = 0101 = 0110 = 0111 = 1000 = 1001 = 1010 = 1011 = 1100 = 1101 = 1110 = 1111 Bank 0 FFh 00h Bank 1 Access RAM GPR GPR 1FFh 200h FFh 00h Bank 2 GPR FFh 00h Bank 3 2FFh 300h GPR FFh 00h Bank 4 The second 160 bytes are Special Function Registers (from Bank 15). When a = 1: 3FFh 400h The BSR specifies the bank used by the instruction.
PIC18F87K22 FAMILY FIGURE 6-7: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) BSR(1) 7 0 0 0 0 0 0 0 Bank Select(2) 1 0 000h Data Memory Bank 0 100h Bank 1 200h 300h Bank 2 00h 7 FFh 00h 1 From Opcode(2) 1 11 1 11 1 0 11 11 FFh 00h FFh 00h Bank 3 through Bank 13 E00h Bank 14 F00h FFFh Note 1: 2: 6.3.2 Bank 15 FFh 00h FFh The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank.
PIC18F87K22 FAMILY 6.3.4 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFRs) are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. SFRs start at the top of data memory (FFFh) and extend downward to occupy all of Bank 15 (F00h to FFFh) and the top part of Bank 14 (EF4h to EFFh). A list of these registers is given in Table 6-1 and Table 6-2.
PIC18F87K22 FAMILY TABLE 6-1: Addr. Name F3Fh TMR7H(3) F3Eh TMR7L(3) F3Dh T7CON(3) SPECIAL FUNCTION REGISTER MAP FOR PIC18F87K22 FAMILY (CONTINUED) Name Addr. F3Ch T7GCON(3) Name Addr.
PIC18F87K22 FAMILY TABLE 6-2: Address PIC18F87K22 FAMILY REGISTER FILE SUMMARY (CONTINUED) File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR FE6h POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) ---- ---- FE5h POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) ---- ---- FE4h PREINC1 Uses contents of FSR1 to address data memory – value o
PIC18F87K22 FAMILY TABLE 6-2: Address PIC18F87K22 FAMILY REGISTER FILE SUMMARY (CONTINUED) File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR CCP10IE(3) CCP9IE(3) 0000 0000 FB6h PIE4 CCP8IE CCP7IE CCP6IE CCP5IE CCP4IE CCP3IE FB5h CVRCON CVREN CVROE CVRSS CVR4 CVR3 CVR2 CVR1 CVR0 0000 0000 FB4h CMSTAT CMP3OUT CMP2OUT CMP1OUT — — — — — xxx- ---- FB3h TMR3H Timer3 Register High Byte FB2h TMR3L Timer3 Register Low Byte FB1h T3CON TMR3
PIC18F87K22 FAMILY TABLE 6-2: Address PIC18F87K22 FAMILY REGISTER FILE SUMMARY (CONTINUED) File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR F86h PORTG — — RG5(1) RG4 RG3 RG2 RG1 RG0 --xx xxxx F85h PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 — xxxx xxx- F84h PORTE RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 xxxx xxxx F83h PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx F82h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx F81h PORTB RB7
PIC18F87K22 FAMILY TABLE 6-2: Address PIC18F87K22 FAMILY REGISTER FILE SUMMARY (CONTINUED) File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RTCC Value Low Register Window Based on RTCPTR<1:0> Value on POR, BOR F5Ch RTCVALL F5Bh ALRMCFG ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 0000 0000 F5Ah ALRMRPT ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 0000 0000 F59h ALRMVALH Alarm Value High Register Window Based on APTR<1:0> xxxx xxxx F58h ALRM
PIC18F87K22 FAMILY TABLE 6-2: Address PIC18F87K22 FAMILY REGISTER FILE SUMMARY (CONTINUED) File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR F2Ch CCPTMRS1 C7TSEL1 C7TSEL0 — C6TSEL0 — C5TSEL0 C4TSEL1 C4TSEL0 00-0 -000 F2Bh CCPTMRS2 — — — C10TSEL0(3) — C9TSEL0(3) C8TSEL1 C8TSEL0 ---0 -000 F2Ah REFOCON ROON — ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 0-00 0000 F29h ODCON1 SSP1OD CCP2OD CCP1OD — — — — SSP2OD 000- ---0 CCP10OD(3) CC
PIC18F87K22 FAMILY 6.3.5 STATUS REGISTER The STATUS register, shown in Register 6-2, contains the arithmetic status of the ALU. The STATUS register can be the operand for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, the write to these five bits is disabled. These bits are set or cleared according to the device logic.
PIC18F87K22 FAMILY 6.4 Data Addressing Modes Note: The execution of some instructions in the core PIC18 instruction set are changed when the PIC18 extended instruction set is enabled. For more information, see Section 6.6 “Data Memory and the Extended Instruction Set”. While the program memory can be addressed in only one way, through the Program Counter, information in the data memory space can be addressed in several ways. For most instructions, the addressing mode is fixed.
PIC18F87K22 FAMILY 6.4.3.1 FSR Registers and the INDF Operand mapped in the SFR space, but are not physically implemented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read from INDF1, for example, reads the data at the address indicated by FSR1H:FSR1L. At the core of Indirect Addressing are three sets of registers: FSR0, FSR1 and FSR2. Each represents a pair of 8-bit registers: FSRnH and FSRnL.
PIC18F87K22 FAMILY 6.4.3.2 FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW In addition to the INDF operand, each FSR register pair also has four additional indirect operands. Like INDF, these are “virtual” registers that cannot be indirectly read or written to. Accessing these registers actually accesses the associated FSR register pair, but also performs a specific action on its stored value.
PIC18F87K22 FAMILY 6.6 Data Memory and the Extended Instruction Set Enabling the PIC18 extended instruction set (XINST Configuration bit = 1) significantly changes certain aspects of data memory and its addressing. Using the Access Bank for many of the core PIC18 instructions introduces a new addressing mode for the data memory space. This mode also alters the behavior of Indirect Addressing using FSR2 and its associated operands.
PIC18F87K22 FAMILY FIGURE 6-9: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff) When a = 0 and f 60h: The instruction executes in Direct Forced mode. ‘f’ is interpreted as a location in the Access RAM, between 060h and FFFh. This is the same as locations, F60h to FFFh (Bank 15), of data memory. Locations below 060h are not available in this addressing mode.
PIC18F87K22 FAMILY 6.6.3 MAPPING THE ACCESS BANK IN INDEXED LITERAL OFFSET MODE The use of Indexed Literal Offset Addressing mode effectively changes how the lower part of Access RAM (00h to 5Fh) is mapped. Rather than containing just the contents of the bottom part of Bank 0, this mode maps the contents from Bank 0 and a user-defined “window” that can be located anywhere in the data memory space.
PIC18F87K22 FAMILY 7.0 FLASH PROGRAM MEMORY 7.1 Table Reads and Table Writes The Flash program memory is readable, writable and erasable during normal operation over the entire VDD range. In order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data RAM: A read from program memory is executed on one byte at a time.
PIC18F87K22 FAMILY FIGURE 7-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) TBLPTRU TBLPTRH Table Latch (8-bit) TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: The Table Pointer actually points to one of 64 holding registers; the address of which is determined by TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in Section 7.5 “Writing to Flash Program Memory”. 7.
PIC18F87K22 FAMILY REGISTER 7-1: R/W-x EEPGD EECON1: EEPROM CONTROL REGISTER 1 R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 CFGS — FREE WRERR(1) WREN WR RD bit 7 bit 0 Legend: S = Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Dat
PIC18F87K22 FAMILY 7.2.2 TABLAT – TABLE LATCH REGISTER 7.2.4 The Table Latch (TABLAT) is an eight-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 7.2.3 The TBLPTR is used in reads, writes and erases of the Flash program memory. When a TBLRD is executed, all 22 bits of the TBLPTR determine which byte is read from program memory into the TABLAT.
PIC18F87K22 FAMILY 7.3 TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, the TBLPTR can be modified automatically for the next table read operation. Reading the Flash Program Memory The TBLRD instruction is used to retrieve data from program memory and places it into data RAM. Table reads from program memory are performed, one byte at a time. FIGURE 7-4: The internal program memory is typically organized by words.
PIC18F87K22 FAMILY 7.4 Erasing Flash Program Memory The erase blocks are: • PIC18FX5K22 and PIC18FX6K22 – 32 words or 64 bytes • PIC18FX7K22 – 64 words or 128 bytes Word erase in the Flash array is not supported. When initiating an erase sequence from the microcontroller itself, a block of 64 or 128 bytes of program memory is erased. The Most Significant 16 bits of the TBLPTR<21:6> point to the block being erased. The TBLPTR<5:0> bits are ignored. The EECON1 register commands the erase operation.
PIC18F87K22 FAMILY 7.5 The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long write cycle. The long write is terminated by the internal programming timer. Writing to Flash Program Memory The programming blocks are: • PIC18FX5K22 and PIC18FX6K22 – 32 words or 64 bytes • PIC18FX7K22 – 64 words or 128 bytes Word or byte programming is not supported. Table writes are used internally to load the holding registers needed to program the Flash memory.
PIC18F87K22 FAMILY 7.5.1 FLASH PROGRAM MEMORY WRITE SEQUENCE The sequence of events for programming an internal program memory location should be: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Read the 64 or 128 bytes into RAM. Update the data values in RAM as necessary. Load the Table Pointer register with the address being erased. Execute the row erase procedure. Load the Table Pointer register with the address of the first byte being written.
PIC18F87K22 FAMILY EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF SIZE_OF_BLOCK COUNTER BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; number of bytes in erase block TBLRD*+ MOVF MOVWF DECFSZ BRA TABLAT, W POSTINC0 COUNTER READ_BLOCK MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF DATA_ADDR_HIGH FSR0H DATA_ADDR_LOW FSR0L NEW_DATA_LOW POSTINC0 NEW_DATA_HIGH INDF0
PIC18F87K22 FAMILY EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED) PROGRAM_MEMORY BSF BCF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF BCF Required Sequence 7.5.
PIC18F87K22 FAMILY 8.0 EXTERNAL MEMORY BUS Note: The External Memory Bus implemented on 64-pin devices. is not The External Memory Bus (EMB) allows the device to access external memory devices (such as Flash, EPROM or SRAM) as program or data memory. It supports both 8 and 16-Bit Data Width modes and three address widths of up to 20 bits. TABLE 8-1: The bus is implemented with 28 pins, multiplexed across four I/O ports.
PIC18F87K22 FAMILY 8.1 External Memory Bus Control The operation of the interface is controlled by the MEMCON register (Register 8-1). This register is available in all program memory operating modes except Microcontroller mode. In this mode, the register is disabled and cannot be written to. The EBDIS bit (MEMCON<7>) controls the operation of the bus and related port functions.
PIC18F87K22 FAMILY 8.2 8.2.1 Address and Data Width The PIC18F87K22 family of devices can be independently configured for different address and data widths on the same memory bus. Both address and data width are set by Configuration bits in the CONFIG3L register. As Configuration bits, this means that these options can only be configured by programming the device and are not controllable in software. The BW bit selects an 8-bit or 16-bit data bus width.
PIC18F87K22 FAMILY 8.3 Wait States While it may be assumed that external memory devices will operate at the microcontroller clock rate, this is often not the case. In fact, many devices require longer times to write or retrieve data than the time allowed by the execution of table read or table write operations. To compensate for this, the External Memory Bus can be configured to add a fixed delay to each table operation using the bus. Wait states are enabled by setting the WAIT Configuration bit.
PIC18F87K22 FAMILY 8.6.1 16-BIT BYTE WRITE MODE During a TBLWT instruction cycle, the TABLAT data is presented on the upper and lower bytes of the AD<15:0> bus. The appropriate WRH or WRL control line is strobed on the LSb of the TBLPTR. Figure 8-1 shows an example of 16-Bit Byte Write mode for PIC18F87K22 family devices. This mode is used for two separate 8-bit memories connected for 16-bit operation. This generally includes basic EPROM and Flash devices.
PIC18F87K22 FAMILY 8.6.2 16-BIT WORD WRITE MODE Figure 8-2 shows an example of 16-Bit Word Write mode for PIC18F87K22 family devices. This mode is used for word-wide memories, which includes some of the EPROM and Flash type memories. This mode allows opcode fetches and table reads from all forms of 16-bit memory, and table writes to any type of word-wide external memories. This method makes a distinction between TBLWT cycles to even or odd addresses.
PIC18F87K22 FAMILY 8.6.3 16-BIT BYTE SELECT MODE Figure 8-3 shows an example of 16-Bit Byte Select mode. This mode allows table write operations to word-wide external memories with byte selection capability. This generally includes both word-wide Flash and SRAM devices. During a TBLWT cycle, the TABLAT data is presented on the upper and lower byte of the AD<15:0> bus. The WRH signal is strobed for each write cycle; the WRL pin is not used.
PIC18F87K22 FAMILY 8.6.4 16-BIT MODE TIMING The presentation of control signals on the External Memory Bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure 8-4 and Figure 8-5.
PIC18F87K22 FAMILY 8.7 will enable one byte of program memory for a portion of the instruction cycle, then BA0 will change and the second byte will be enabled to form the 16-bit instruction word. The Least Significant bit of the address, BA0, must be connected to the memory devices in this mode. The Chip Enable (CE) signal is active at any time that the microcontroller accesses external memory, whether reading or writing. It is inactive (asserted high) whenever the device is in Sleep mode.
PIC18F87K22 FAMILY 8.7.1 8-BIT MODE TIMING The presentation of control signals on the External Memory Bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure 8-7 and Figure 8-8.
PIC18F87K22 FAMILY 8.8 In Sleep and Idle modes, the microcontroller core does not need to access data; bus operations are suspended. The state of the external bus is frozen, with the address/data pins, and most of the control pins, holding at the same state they were in when the mode was invoked. The only potential changes are to the CE, LB and UB pins, which are held at logic high. Operation in Power-Managed Modes In alternate, power-managed Run modes, the external bus continues to operate normally.
PIC18F87K22 FAMILY NOTES: DS39960D-page 132 2009-2011 Microchip Technology Inc.
PIC18F87K22 FAMILY 9.0 DATA EEPROM MEMORY The data EEPROM is a nonvolatile memory array, separate from the data RAM and program memory, that is used for long-term storage of program data. It is not directly mapped in either the register file or program memory space, but is indirectly addressed through the Special Function Registers (SFRs). The EEPROM is readable and writable during normal operation over the entire VDD range.
PIC18F87K22 FAMILY REGISTER 9-1: R/W-x EEPGD EECON1: DATA EEPROM CONTROL REGISTER 1 R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 CFGS — FREE WRERR(1) WREN WR RD bit 7 bit 0 Legend: S = Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Progra
PIC18F87K22 FAMILY 9.3 Reading the Data EEPROM Memory To read a data memory location, the user must write the address to the EEADRH:EEADR register pair, clear the EEPGD control bit (EECON1<7>) and then set control bit, RD (EECON1<0>). The data is available in the EEDATA register after one cycle; therefore, it can be read after one NOP instruction. EEDATA will hold this value until another read operation or until it is written to by the user (during a write operation).
PIC18F87K22 FAMILY EXAMPLE 9-1: MOVLW MOVWF MOVLW MOVWF BCF BCF BSF NOP MOVF EXAMPLE 9-2: Required Sequence DS39960D-page 136 DATA EEPROM READ DATA_EE_ADDRH EEADRH DATA_EE_ADDR EEADR EECON1, EEPGD EECON1, CFGS EECON1, RD ; ; ; ; ; ; ; EEDATA, W ; W = EEDATA Upper bits of Data Memory Address to read Lower bits of Data Memory Address to read Point to DATA memory Access EEPROM EEPROM Read DATA EEPROM WRITE MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF BCF BCF BSF DATA_EE_ADDRH EEADRH DATA_EE_ADDR EEADR DATA_EE
PIC18F87K22 FAMILY 9.6 Operation During Code-Protect Data EEPROM memory has its own code-protect bits in the Configuration Words. External read and write operations are disabled if code protection is enabled. The microcontroller itself can both read and write to the internal data EEPROM, regardless of the state of the code-protect Configuration bit. Refer to Section 28.0 “Special Features of the CPU” for additional information. 9.
PIC18F87K22 FAMILY TABLE 9-1: Name INTCON EEADRH REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF EEPROM Address Register High Byte EEADR EEPROM Address Register Low Byte EEDATA EEPROM Data Register EECON2 EEPROM Control Register 2 (not a physical register) EEPGD CFGS — FREE WRERR WREN WR RD IPR6 — — — EEIP — CMP3IP CMP2IP CMP1IP PIR6 — — — EEIF — CMP3IF CMP2IF
PIC18F87K22 FAMILY 10.0 8 x 8 HARDWARE MULTIPLIER 10.1 Introduction All PIC18 devices include an 8 x 8 hardware multiplier as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, PRODH:PRODL. The multiplier’s operation does not affect any flags in the STATUS register.
PIC18F87K22 FAMILY Example 10-3 shows the sequence to do a 16 x 16 unsigned multiplication. Equation 10-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0).
PIC18F87K22 FAMILY 11.0 INTERRUPTS Members of the PIC18F87K22 family of devices have multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high-priority level or a low-priority level. The high-priority interrupt vector is at 0008h and the low-priority interrupt vector is at 0018h. High-priority interrupt events will interrupt any low-priority interrupts that may be in progress.
PIC18F87K22 FAMILY FIGURE 11-1: PIC18F87K22 FAMILY INTERRUPT LOGIC PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7,5:0> PIE2<7,5:0> IPR2<7,5:0> PIR3<7,5> PIE3<7,5> IPR3<7,5> PIR4<7:0> PIE4<7:0> IPR4<7:0> PIR5<7:0> PIE5<7:0> IPR5<7:0> Wake-up if in Idle or Sleep modes TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP Interrupt to CPU Vector to Location 0008h GIE/GIEH IPEN PIR6<4, 2:0> PIE6<4, 2:0> IPR6<4, 2:0> IPEN PEIE/GIEL IPEN High-Priority Inte
PIC18F87K22 FAMILY 11.1 INTCON Registers Note: The INTCON registers are readable and writable registers that contain various enable, priority and flag bits. REGISTER 11-1: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.
PIC18F87K22 FAMILY REGISTER 11-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual TRIS register values bit
PIC18F87K22 FAMILY REGISTER 11-3: INTCON3: INTERRUPT CONTROL REGISTER 3 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low
PIC18F87K22 FAMILY 11.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are six Peripheral Interrupt Request (Flag) registers (PIR1 through PIR6). REGISTER 11-4: Note 1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE (INTCON<7>).
PIC18F87K22 FAMILY REGISTER 11-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIF — SSP2IF BCL2IF BCL1IF HLVDIF TMR3IF TMR3GIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = Device oscillator failed, clock input has changed to INTOSC (must be cleared in so
PIC18F87K22 FAMILY REGISTER 11-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 R/W-0 U-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 TMR5GIF — RC2IF TX2IF CTMUIF CCP2IF CCP1IF RTCCIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TMR5GIF: Timer5 Gate Interrupt Flag bit 1 = Timer gate interrupt occurred (must be cleared in software) 0 = No timer gate interrupt occ
PIC18F87K22 FAMILY REGISTER 11-7: R/W-0 CCP10IF (1) PIR4: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 4 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CCP9IF(1) CCP8IF CCP7IF CCP6IF CCP5IF CCP4IF CCP3IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-1 CCP<10:4>IF: CCP<10:4> Interrupt Flag bits(1) Capture Mode: 1 = A TMR register capture occurred (must be cleared in
PIC18F87K22 FAMILY REGISTER 11-8: PIR5: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 5 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TMR7GIF(1) TMR12IF(1) TMR10IF(1) TMR8IF TMR7IF(1) TMR6IF TMR5IF TMR4IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TMR7GIF: TMR7 Gate Interrupt Flag bits(1) 1 = TMR gate interrupt occurred (bit must be cleared in software)
PIC18F87K22 FAMILY REGISTER 11-9: PIR6: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 6 U-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 — — — EEIF — CMP3IF CMP2IF CMP1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4 EEIF: Data EEDATA/Flash Write Operation Interrupt Flag bit 1 = The write operation is complete (must be cleared in software) 0 = The wri
PIC18F87K22 FAMILY 11.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are six Peripheral Interrupt Enable registers (PIE1 through PIE6). When IPEN (RCON<7>) = 0, the PEIE bit must be set to enable any of these peripheral interrupts.
PIC18F87K22 FAMILY REGISTER 11-11: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIE — SSP2IE BCL2IE BCL1IE HLVDIE TMR3IE TMR3GIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 Unimplemented: Read as ‘0’ bit 5 SSP2IE: Master Synchronous Serial Port 2 Inte
PIC18F87K22 FAMILY REGISTER 11-12: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 R/W-0 U-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 TMR5GIE — RC2IE TX2IE CTMUIE CCP2IE CCP1IE RTCCIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR5GIE: Timer5 Gate Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 Unimplemented: Read as ‘0’ bit 5 RC2IE: EUSART Receive Interrupt Enable bit 1 = Enabled
PIC18F87K22 FAMILY REGISTER 11-14: PIE5: PERIPHERAL INTERRUPT ENABLE REGISTER 5 R/W-0 (1) TMR7GIE R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TMR12IE(1) TMR10IE(1) TMR8IE TMR7IE(1) TMR6IE TMR5IE TMR4IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR7GIE: TMR7 Gate Interrupt Enable bit(1) 1 = Enabled 0 = Disabled bit 6 TMR12IE: TMR12 to PR12 Match Interrupt Enable bit(1) 1 = Ena
PIC18F87K22 FAMILY REGISTER 11-15: PIE6: PERIPHERAL INTERRUPT ENABLE REGISTER 6 U-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 — — — EEIE — CMP3IE CMP2IE CMP1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4 EEIE: Data EEDATA/Flash Write Operation Enable bit 1 = Interrupt is enabled 0 = interrupt is disabled bit 3 Unimplemented: Read as ‘0’ bit 2
PIC18F87K22 FAMILY 11.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are six Peripheral Interrupt Priority registers (IPR1 through IPR6). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit (RCON<7>) be set.
PIC18F87K22 FAMILY REGISTER 11-17: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 OSCFIP — SSP2IP BCL2IP BCL1IP HLVDIP TMR3IP TMR3GIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 Unimplemented: Read as ‘0’ bit 5 SSP2IP: Master Synchronous Seri
PIC18F87K22 FAMILY REGISTER 11-18: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 R/W-1 U-0 R-1 R-1 R/W-1 R/W-1 R/W-1 R/W-1 TMR5GIP — RC2IP TX2IP CTMUIP CCP2IP CCP1IP RTCCIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR5GIP: Timer5 Gate interrupt Priority bit 1 = High priority 0 = Low priority bit 6 Unimplemented: Read as ‘0’ bit 5 RC2IP: EUSART Receive Priority Flag bit
PIC18F87K22 FAMILY REGISTER 11-20: IPR5: PERIPHERAL INTERRUPT PRIORITY REGISTER 5 R/W-1 (1) TMR7GIP R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TMR12IP(1) TMR10IP(1) TMR8IP TMR7IP(1) TMR6IP TMR5IP TMR4IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR7GIP: TMR7 Gate Interrupt Priority bit(1) 1 = High priority 0 = Low priority bit 6 TMR12IP: TMR12 to PR12 Match Interrupt Priorit
PIC18F87K22 FAMILY REGISTER 11-21: IPR6: PERIPHERAL INTERRUPT PRIORITY REGISTER 6 U-0 U-0 U-0 R/W-1 U-0 R/W-1 R/W-1 R/W-1 — — — EEIP — CMP3IP CMP2IP CMP1IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4 EEIP: EE Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 Unimplemented: Read as ‘0’ bit 2 CMP3IP: CMP3 Interrupt Priority b
PIC18F87K22 FAMILY 11.5 RCON Register The RCON register contains the bits used to determine the cause of the last Reset, or wake-up from Idle or Sleep modes. RCON also contains the bit that enables interrupt priorities (IPEN).
PIC18F87K22 FAMILY 11.6 INTx Pin Interrupts 11.7 External interrupts on the RB0/INT0, RB1/INT1, RB2/INT2 and RB3/INT3 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge. If that bit is clear, the trigger is on the falling edge. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit, INTxIF, is set. This interrupt can be disabled by clearing the corresponding enable bit, INTxIE.
PIC18F87K22 FAMILY TABLE 11-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF PIR1 PSPIP ADIF RC1IF TX1IF SSP1IF TMR1GIF TMR2IF TMR1IF PIR2 OSCFIF — SSP2IF BCL2IF BCL1IF HLVDIF TMR3IF TMR3GIF INTCON PIR3 TMR5GIF — RC
PIC18F87K22 FAMILY 12.0 I/O PORTS 12.1 Depending on the device selected and features enabled, there are up to nine ports available. Some pins of the I/O ports are multiplexed with an alternate function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin.
PIC18F87K22 FAMILY REGISTER 12-1: PADCFG1: PAD CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 RDPU REPU RJPU(2) — — RTSECSEL1(1) RTSECSEL0(1) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RDPU: PORTD Pull-up Enable bit 1 = PORTD pull-up resistors are enabled by individual port latch values 0 = All PORTD pull-up resistors are disabled bit
PIC18F87K22 FAMILY 12.1.3 OPEN-DRAIN OUTPUTS FIGURE 12-2: The output pins for several peripherals are also equipped with a configurable, open-drain output option. This allows the peripherals to communicate with external digital logic, operating at a higher voltage level, without the use of level translators. USING THE OPEN-DRAIN OUTPUT (USART SHOWN AS EXAMPLE) 3.
PIC18F87K22 FAMILY REGISTER 12-3: R/W-0 (1) CCP10OD ODCON2: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CCP9OD(1) CCP8OD CCP7OD CCP6OD CCP5OD CCP4OD CCP3OD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CCP10OD: CCP10 Open-Drain Output Enable bit(1) 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled bit 6 CCP9OD: CCP
PIC18F87K22 FAMILY REGISTER 12-4: R/W-0 U2OD ODCON3: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 3 R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U1OD — — — — — CTMUDS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 U2OD: EUSART2 Open-Drain Output Enable bit 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled bit 6 U1OD: EUSART1 Open-Drain Output Enable bit 1 = Open-drain capab
PIC18F87K22 FAMILY 12.2 PORTA, TRISA and LATA Registers PORTA is an 8-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are TRISA and LATA. RA4/T0CKI is a Schmitt Trigger input. All other PORTA pins have TTL input levels and full CMOS output drivers. RA5 and RA<3:0> are multiplexed with analog inputs for the A/D Converter. The operation of the analog inputs as A/D Converter inputs is selected by clearing or setting the ANSEL control bits in the ANCON1 register.
PIC18F87K22 FAMILY TABLE 12-1: PORTA FUNCTIONS Pin Name Function TRIS Setting I/O I/O Type RA0/AN0/ULPWU RA0 0 O DIG 1 I TTL PORTA<0> data input; disabled when analog input is enabled. AN0 1 I ANA A/D Input Channel 0. Default input configuration on POR; does not affect digital output. ULPWU 1 I ANA Ultra Low-Power Wake-up input. RA1 0 O DIG LATA<1> data output; not affected by analog input. 1 I TTL PORTA<1> data input; disabled when analog input is enabled.
PIC18F87K22 FAMILY 12.3 PORTB, TRISB and LATB Registers PORTB is an eight-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are TRISB and LATB. All pins on PORTB are digital only.
PIC18F87K22 FAMILY TABLE 12-3: PORTB FUNCTIONS (CONTINUED) Pin Name Function TRIS Setting I/O I/O Type RB3 0 O DIG 1 I TTL PORTB<3> data input; weak pull-up when RBPU bit is cleared. INT3 1 I ST External Interrupt 3 input. x I ST CTMU Edge 2 input. 0 O DIG ECCP2 compare output and ECCP2 PWM output. Takes priority over port data. 1 I ST ECCP2 capture input. P2A 0 O DIG ECCP2 Enhanced PWM output, Channel A.
PIC18F87K22 FAMILY 12.4 PORTC, TRISC and LATC Registers PORTC is an eight-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are TRISC and LATC. Only PORTC pins, RC2 through RC7, are digital only pins. PORTC is multiplexed with ECCP, MSSP and EUSART peripheral functions (Table 12-5). The pins have Schmitt Trigger input buffers. The pins for ECCP, SPI and EUSART are also configurable for open-drain output whenever these functions are active.
PIC18F87K22 FAMILY TABLE 12-5: Pin Name RC3/SCK1/ SCL1 PORTC FUNCTIONS (CONTINUED) Function TRIS Setting I/O I/O Type RC3 0 O DIG SCK1 1 I ST PORTC<3> data input. 0 O DIG SPI clock output (MSSP module); takes priority over port data. I ST SPI clock input (MSSP module). 0 O DIG I2C clock output (MSSP module); takes priority over port data. 1 I I2C I2C clock input (MSSP module); input type depends on module setting. 0 O DIG LATC<4> data output. 1 I ST PORTC<4> data input.
PIC18F87K22 FAMILY 12.5 PORTD, TRISD and LATD Registers PORTD is an 8-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are TRISD and LATD. All pins on PORTD are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. These pins are configured as digital inputs on any device Reset. Note: Each of the PORTD pins has a weak internal pull-up. A single control bit can turn off all the pull-ups.
PIC18F87K22 FAMILY TABLE 12-7: PORTD FUNCTIONS (CONTINUED) Pin Name Function TRIS Setting I/O I/O Type RD3/PSP3/AD3 RD3 0 O DIG LATD<3> data output. 1 I ST PORTD<3> data input. PSP3(1) x I/O TTL Parallel Slave Port data. AD3(2) x I/O TTL External Memory Address/Data 3. RD4 0 O DIG LATD<4> data output. 1 I ST PORTD<4> data input. PSP4(1) x I/O TTL Parallel Slave Port data. AD4(2) x I/O TTL External Memory Address/Data 4.
PIC18F87K22 FAMILY 12.6 PORTE, TRISE and LATE Registers PORTE is an eight-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are TRISE and LATE. All pins on PORTE are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. The RE7 pin is also configurable for open-drain output when ECCP2 is active on this pin.
PIC18F87K22 FAMILY TABLE 12-9: Pin Name RE2/CS/P2B/ CCP10/AD10 RE3/P3C/ CCP9/REFO/ AD11 RE4/P3B/ CCP8/AD12 PORTE FUNCTIONS (CONTINUED) Function TRIS Setting I/O I/O Type RE2 0 O DIG LATE<2> data output. PORTE<2> data input. 1 I ST CS x I TTL P2B 0 O — CCP10 1 I/O ST Capture 10 input/Compare 10 output/PWM10 output. AD10(2) x O DIG External memory interface, Address/Data Bit 10 output. x I TTL External memory interface, Data Bit 10 input. 0 O DIG LATE<3> data output.
PIC18F87K22 FAMILY TABLE 12-9: Pin Name PORTE FUNCTIONS (CONTINUED) Function TRIS Setting I/O I/O Type RE7 0 O DIG RE7/ECCP2/ P2A/AD15 ECCP2(1) Legend: Note 1: 2: Description LATE<7> data output. 1 I ST PORTE<7> data input. 0 O DIG ECCP2 compare/PWM output; takes priority over port data. 1 I ST ECCP2 capture input. P2A 0 O — ECCP2 PWM Output A. May be configured for tri-state during Enhanced PWM shutdown event.
PIC18F87K22 FAMILY 12.7 PORTF, LATF and TRISF Registers EXAMPLE 12-6: PORTF is a 7-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are TRISF and LATF. All pins on PORTF are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. CLRF PORTF CLRF LATF Pins, RF1 through RF6, may be used as comparator inputs or outputs by setting the appropriate bits in the CMCON register.
PIC18F87K22 FAMILY TABLE 12-11: PORTF FUNCTIONS (CONTINUED) Pin Name RF6/AN11/C1INA Function TRIS Setting I/O I/O Type RF6 0 O DIG 1 I ST PORTF<6> data input; disabled when analog input is enabled. 1 I ANA A/D Input Channel 11 and Comparator C1- input. Default input configuration on POR; does not affect digital output. AN11 RF7/AN5/SS1 Legend: Description LATF<6> data output; not affected by analog input. C1INA 1 I ANA Comparator 1 Input A.
PIC18F87K22 FAMILY 12.8 PORTG, TRISG and LATG Registers PORTG is a 5-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are TRISG and LATG. PORTG is multiplexed with the AUSART and CCP, ECCP, Analog, Comparator, RTCC and Timer input functions (Table 12-13). When operating as I/O, all PORTG pins have Schmitt Trigger input buffers. The open-drain functionality for the CCPx and UART can be configured using ODCONx.
PIC18F87K22 FAMILY TABLE 12-13: PORTG FUNCTIONS (CONTINUED) Pin Name Function TRIS Setting I/O I/O Type RG2 0 O DIG LATG<2> data output. PORTG<2> data input. RG2/RX2/DT2/ AN18/C3INA RG3/CCP4/AN17/ P3D/C3INB 1 I ST RX2 1 I ST Asynchronous serial receive data input (EUSART module). DT2 1 O DIG Synchronous serial data output (EUSART module); takes priority over port data. 1 I ST Synchronous serial data input (EUSART module); user must configure as an input.
PIC18F87K22 FAMILY 12.9 Note: EXAMPLE 12-8: PORTH, LATH and TRISH Registers PORTH is available only on the 80-pin devices. PORTH is an 8-bit wide, bidirectional I/O port. The corresponding Data Direction and Output Latch registers are TRISH and LATH. All pins on PORTH are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output.
PIC18F87K22 FAMILY TABLE 12-15: PORTH FUNCTIONS (CONTINUED) Pin Name Function TRIS Setting I/O I/O Type RH4 0 O DIG LATH<4> data output. 1 I ST PORTH<4> data input. 0 O DIG CCP9 compare/PWM output; takes priority over port data. 1 I ST CCP9 capture input. P3C 0 O — ECCP3 PWM Output C. May be configured for tri-state during Enhanced PWM. AN12 1 I ANA A/D Input Channel 12. Default input configuration on POR; does not affect digital input. C2INC x I ANA Comparator 2 Input C.
PIC18F87K22 FAMILY TABLE 12-16: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PORTH(1) RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0 LATH7 LATH6 LATH5 LATH4 LATH3 LATH2 LATH1 LATH0 LATH(1) TRISH (1) ANCON1 ANCON2 ODCON2 Note 1: 2: TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 ANSEL15 ANSEL14 ANSEL13 ANSEL12 ANSEL11 ANSEL10 ANSEL9 ANSEL8 ANSEL23 ANSEL22 ANSEL21 ANSEL20 ANSEL19 ANSEL18 ANSEL17 ANSEL16 CCP8OD CC
PIC18F87K22 FAMILY TABLE 12-17: PORTJ FUNCTIONS Pin Name Function TRIS Setting I/O I/O Type RJ0 0 O DIG RJ0/ALE RJ1/OE RJ2/WRL RJ3/WRH RJ4/BA0 RJ5/CE RJ6/LB RJ7/UB LATJ<0> data output. 1 I ST PORTJ<0> data input. ALE x O DIG External memory interface address latch enable control output; takes priority over digital I/O. RJ1 0 O DIG LATJ<1> data output. 1 I ST PORTJ<1> data input.
PIC18F87K22 FAMILY 12.11 Parallel Slave Port PORTD can function as an 8-bit-wide Parallel Slave Port (PSP), or microprocessor port, when control bit, PSPMODE (PSPCON<4>), is set. The port is asynchronously readable and writable by the external world through the RD control input pin (RE0/P2D/RD/AD8) and WR control input pin (RE1/P2C/WR/AD9). Note: The Parallel Slave Port is available only in Microcontroller mode. The PSP can directly interface to an 8-bit microprocessor data bus.
PIC18F87K22 FAMILY REGISTER 12-5: PSPCON: PARALLEL SLAVE PORT CONTROL REGISTER R-0 R-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 IBF OBF IBOV PSPMODE — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IBF: Input Buffer Full Status bit 1 = A word has been received and is waiting to be read by the CPU 0 = No word has been received bit 6 OBF: Output Buffer Full Status b
PIC18F87K22 FAMILY FIGURE 12-5: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 12-19: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Name PORTD Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 PORTE RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 LATE LATE7 L
PIC18F87K22 FAMILY NOTES: DS39960D-page 192 2009-2011 Microchip Technology Inc.
PIC18F87K22 FAMILY 13.0 TIMER0 MODULE The Timer0 module incorporates the following features: • Software-selectable operation as a timer or counter in both 8-bit or 16-bit modes • Readable and writable registers • Dedicated 8-bit, software programmable prescaler • Selectable clock source (internal or external) • Edge select for external clock • Interrupt-on-overflow REGISTER 13-1: The T0CON register (Register 13-1) controls all aspects of the module’s operation, including the prescale selection.
PIC18F87K22 FAMILY 13.1 Timer0 Operation Timer0 can operate as either a timer or a counter. The mode is selected with the T0CS bit (T0CON<5>). In Timer mode (T0CS = 0), the module increments on every clock by default unless a different prescaler value is selected (see Section 13.3 “Prescaler”). If the TMR0 register is written to, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register.
PIC18F87K22 FAMILY 13.3 13.3.1 Prescaler An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not directly readable or writable. Its value is set by the PSA and T0PS<2:0> bits (T0CON<3:0>), which determine the prescaler assignment and prescale ratio. The prescaler assignment is fully under software control and can be changed “on-the-fly” during program execution. 13.4 Clearing the PSA bit assigns the prescaler to the Timer0 module.
PIC18F87K22 FAMILY NOTES: DS39960D-page 196 2009-2011 Microchip Technology Inc.
PIC18F87K22 FAMILY 14.0 TIMER1 MODULE The Timer1 timer/counter module incorporates these features: • Software-selectable operation as a 16-bit timer or counter • Readable and writable 8-bit registers (TMR1H and TMR1L) • Selectable clock source (internal or external) with device clock or SOSC oscillator internal options • Interrupt-on-overflow • Reset on ECCP Special Event Trigger • Timer with gated control REGISTER 14-1: Figure 14-1 displays a simplified block diagram of the Timer1 module.
PIC18F87K22 FAMILY 14.1 Timer1 Gate Control Register The Timer1 Gate Control register (T1GCON), displayed in Register 14-2, is used to control the Timer1 gate.
PIC18F87K22 FAMILY 14.2 14.3.2 Timer1 Operation The Timer1 module is an 8 or 16-bit incrementing counter that is accessed through the TMR1H:TMR1L register pair. When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module can be used as either a timer or counter. It increments on every selected edge of the external source.
PIC18F87K22 FAMILY FIGURE 14-1: TIMER1 BLOCK DIAGRAM T1GSS<1:0> T1G 00 From TMR2 Match PR2 01 From Comparator 1 Output 10 From Comparator 2 Output 11 T1GSPM 0 T1G_IN T1GVAL 0 Single Pulse TMR1ON T1GPOL D Q CK R Q 1 Acq.
PIC18F87K22 FAMILY 14.4 Timer1 16-Bit Read/Write Mode FIGURE 14-2: Timer1 can be configured for 16-bit reads and writes. When the RD16 control bit (T1CON<1>) is set, the address for TMR1H is mapped to a buffer register for the high byte of Timer1. A read from TMR1L loads the contents of the high byte of Timer1 into the Timer1 High Byte Buffer register.
PIC18F87K22 FAMILY The Lower Drive Level mode is highly optimized for extremely low-power consumption. It is not intended to drive all types of 32.768 kHz crystals. In the Low Drive Level mode, the crystal oscillator circuit may not work correctly if excessively large discrete capacitors are placed on the SOSCO and SOSCI pins. This mode is designed to work only with discrete capacitances of approximately 3 pF-10 pF on each pin.
PIC18F87K22 FAMILY 14.7 Resetting Timer1 Using the ECCP Special Event Trigger If ECCP modules are configured to use Timer1 and to generate a Special Event Trigger in Compare mode (CCPxM<3:0> = 1011), this signal will reset Timer1. The trigger from ECCP2 will also start an A/D conversion, if the A/D module is enabled. (For more information, see Section 20.3.4 “Special Event Trigger”.) To take advantage of this feature, the module must be configured as either a timer or a synchronous counter.
PIC18F87K22 FAMILY FIGURE 14-4: TIMER1 GATE COUNT ENABLE MODE TMR1GE T1GPOL T1G_IN T1CKI T1GVAL Timer1 14.8.2 N TIMER1 GATE SOURCE SELECTION The Timer1 gate source can be selected from one of four sources. Source selection is controlled by the T1GSSx (T1GCON<1:0>) bits (see Table 14-4).
PIC18F87K22 FAMILY 14.8.3 TIMER1 GATE TOGGLE MODE When Timer1 Gate Toggle mode is enabled, it is possible to measure the full cycle length of a Timer1 gate signal, as opposed to the duration of a single level pulse. The Timer1 gate source is routed through a flip-flop that changes state on every incrementing edge of the signal. (For timing details, see Figure 14-5.) FIGURE 14-5: The T1GVAL bit (T1GCON<2>) indicates when the Toggled mode is active and the timer is counting.
PIC18F87K22 FAMILY 14.8.4 TIMER1 GATE SINGLE PULSE MODE When Timer1 Gate Single Pulse mode is enabled, it is possible to capture a single pulse gate event. Timer1 Gate Single Pulse mode is enabled by setting the T1GSPM bit (T1GCON<4>) and the T1GGO/T1DONE bit (T1GCON<3>). The Timer1 will be fully enabled on the next incrementing edge. On the next trailing edge of the pulse, the T1GGO/ T1DONE bit will automatically be cleared.
PIC18F87K22 FAMILY FIGURE 14-7: TIMER1 GATE SINGLE PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM Cleared by Hardware on Falling Edge of T1GVAL Set by Software T1GGO/ T1DONE Counting Enabled on Rising Edge of T1G T1G_IN T1CKI T1GVAL Timer1 TABLE 14-5: Name INTCON N+4 N+3 Set by Hardware on Falling Edge of T1GVAL Cleared by Software RTCCIF N+2 N+1 N Cleared by Software REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GI
PIC18F87K22 FAMILY NOTES: DS39960D-page 208 2009-2011 Microchip Technology Inc.
PIC18F87K22 FAMILY 15.
PIC18F87K22 FAMILY 15.2 Timer2 Interrupt 15.3 Timer2 can also generate an optional device interrupt. The Timer2 output signal (TMR2 to PR2 match) provides the input for the 4-bit output counter/postscaler. This counter generates the TMR2 match interrupt flag, which is latched in TMR2IF (PIR1<1>). The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE (PIE1<1>).
PIC18F87K22 FAMILY 16.0 TIMER3/5/7 MODULES The Timer3/5/7 timer/counter modules incorporate these features: • Software-selectable operation as a 16-bit timer or counter • Readable and writable eight-bit registers (TMRxH and TMRxL) • Selectable clock source (internal or external) with device clock or SOSC oscillator internal options • Interrupt-on-overflow • Module Reset on ECCP Special Event Trigger A simplified block diagram of the Timer3/5/7 module is shown in Figure 16-1.
PIC18F87K22 FAMILY REGISTER 16-1: TxCON: TIMERx CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TMRxCS1 TMRxCS0 TxCKPS1 TxCKPS0 SOSCEN TxSYNC RD16 TMRxON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 TMRxCS<1:0>: Timerx Clock Source Select bits 10 = Timer1 clock source depends on the SOSCEN bit: SOSCEN = 0: External clock from the T1CKI pi
PIC18F87K22 FAMILY 16.1 Timer3/5/7 Gate Control Register The Timer3/5/7 Gate Control register (TxGCON), provided in Register 14-2, is used to control the Timerx gate.
PIC18F87K22 FAMILY REGISTER 16-3: OSCCON2: OSCILLATOR CONTROL REGISTER 2 U-0 R-0 U-0 U-0 R/W-0 U-0 R-x R/W-0 — SOSCRUN — — SOSCGO — MFIOFS MFIOSEL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 SOSCRUN: SOSC Run Status bit 1 = System clock comes from a secondary SOSC 0 = System clock comes from an oscillator other than SOSC
PIC18F87K22 FAMILY 16.2 The operating mode is determined by the clock select bits, TMRxCSx (TxCON<7:6>). When the TMRxCSx bits are cleared (= 00), Timer3/5/7 increments on every internal instruction cycle (FOSC/4). When TMRxCSx = 01, the Timer3/5/7 clock source is the system clock (FOSC), and when it is ‘10’, Timer3/5/7 works as a counter from the external clock from the TxCKI pin (on the rising edge after the first falling edge) or the SOSC oscillator.
PIC18F87K22 FAMILY 16.3 Timer3/5/7 16-Bit Read/Write Mode Timer3/5/7 can be configured for 16-bit reads and writes (see Figure 16.3). When the RD16 control bit (TxCON<1>) is set, the address for TMRxH is mapped to a buffer register for the high byte of Timer3/5/7. A read from TMRxL will load the contents of the high byte of Timer3/5/7 into the Timerx High Byte Buffer register.
PIC18F87K22 FAMILY 16.5 When Timerx Gate Enable mode is enabled, Timer3/5/7 will increment on the rising edge of the Timer3/5/7 clock source. When Timerx Gate Enable mode is disabled, no incrementing will occur and Timer3/5/7 will hold the current count. See Figure 16-2 for timing details. Timer3/5/7 Gates Timer3/5/7 can be configured to count freely or the count can be enabled and disabled using the Timer3/5/7 gate circuitry. This is also referred to as the Timer3/5/7 gate count enable.
PIC18F87K22 FAMILY 16.5.2 TIMER3/5/7 GATE SOURCE SELECTION The Timer3/5/7 gate source can be selected from one of four different sources. Source selection is controlled by the TxGSS<1:0> bits (TxGCON<1:0>). The polarity for each available source is also selectable and is controlled by the TxGPOL bit (TxGCON <6>).
PIC18F87K22 FAMILY 16.5.4 TIMER3/5/7 GATE SINGLE PULSE MODE No other gate events will be allowed to increment Timer3/5/7 until the TxGGO/TxDONE bit is once again set in software. When Timer3/5/7 Gate Single Pulse mode is enabled, it is possible to capture a single pulse gate event. Timer3/5/7 Gate Single Pulse mode is first enabled by setting the TxGSPM bit (TxGCON<4>). Next, the TxGGO/TxDONE bit (TxGCON<3>) must be set. Clearing the TxGSPM bit also will clear the TxGGO/ TxDONE bit.
PIC18F87K22 FAMILY FIGURE 16-5: TIMER3/5/7 GATE SINGLE PULSE AND TOGGLE COMBINED MODE TMRxGE TxGPOL TxGSPM TxGTM TxGGO/ Cleared by Hardware on Falling Edge of TxGVAL Set by Software TxDONE Counting Enabled on Rising Edge of TxG TxG_IN TxCKI TxGVAL Timer3/5/7 TMRxGIF 16.5.5 N N+1 Cleared by Software TIMER3/5/7 GATE VALUE STATUS When Timer3/5/7 gate value status is utilized, it is possible to read the most current level of the gate control value.
PIC18F87K22 FAMILY 16.6 Timer3/5/7 Interrupt The TMRx register pair (TMRxH:TMRxL) increments from 0000h to FFFFh and overflows to 0000h. The Timerx interrupt, if enabled, is generated on overflow and is latched in the interrupt flag bit, TMRxIF. Table 16-3 gives each module’s flag bit. TABLE 16-3: TIMER3/5/7 INTERRUPT FLAG BITS Timer Module Flag Bit 3 PIR2<1> 5 PIR5<1> 7 PIR5<3> This interrupt can be enabled or disabled by setting or clearing the TMRxIE bit, respectively.
PIC18F87K22 FAMILY TABLE 16-5: Name INTCON REGISTERS ASSOCIATED WITH TIMER3/5/7 AS A TIMER/COUNTER Bit 7 Bit 6 GIE/GIEH PEIE/GIEL PIR5 TMR7GIF(1) (1) TMR12IF Bit 5 (1) (1) TMR0IE TMR10IF (1) Bit 4 Bit 3 INT0IE RBIE TMR8IF TMR7IF Bit 2 Bit 1 Bit 0 TMR0IF INT0IF RBIF (1) TMR6IF TMR5IF TMR4IF (1) IPR5 TMR7GIP (1) TMR8IP TMR7IP TMR6IP TMR5IP TMR4IP PIE5 TMR7GIE(1) TMR12IE(1) TMR10IE(1) TMR8IE TMR7IE(1) TMR6IE TMR5IE TMR4IE TMR12IP TMR10IP PIE3 TMR5GIE — RC2IE TX2
PIC18F87K22 FAMILY 17.0 TIMER4/6/8/10/12 MODULES The Timer4/6/8/10/12 timer modules have the following features: • • • • • • Eight-bit Timer register (TMRx) Eight-bit Period register (PRx) Readable and writable (all registers) Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) Interrupt on TMRx match of PRx Timer10 and Timer12 are unimplemented for devices with a program memory of 32 Kbytes (PIC18FX5K22).
PIC18F87K22 FAMILY REGISTER 17-1: TxCON: TIMERx CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — TxOUTPS3 TxOUTPS2 TxOUTPS1 TxOUTPS0 TMRxON TxCKPS1 TxCKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-3 TxOUTPS<3:0>: Timerx Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale • • • 1111 = 1:16 Postscale bit
PIC18F87K22 FAMILY TABLE 17-3: Name INTCON REGISTERS ASSOCIATED WITH TIMER4/6/8/10/12 AS A TIMER/COUNTER Bit 7 Bit 6 Bit 5 Bit 4 GIE/GIEH PEIE/GIEL TMR0IE Bit 3 Bit 2 Bit 1 Bit 0 INT0IE RBIE TMR0IF INT0IF RBIF IPR5 TMR7GIP(1) TMR12IP(1) TMR10IP(1) TMR8IP TMR7IP(1) TMR6IP TMR5IP TMR4IP PIR5 TMR7GIF(1) TMR12IF(1) TMR10IF(1) TMR8IF TMR7IF(1) TMR6IF TMR5IF TMR4IF TMR8IE TMR7IE(1) TMR6IE TMR5IE TMR4IE (1) PIE5 TMR7GIE TMR4 TMR12IE (1) TMR10IE Timer4 Register — T4CON T
PIC18F87K22 FAMILY NOTES: DS39960D-page 226 2009-2011 Microchip Technology Inc.
PIC18F87K22 FAMILY 18.0 REAL-TIME CLOCK AND CALENDAR (RTCC) The key features of the Real-Time Clock and Calendar (RTCC) module are: • • • • • • • • • • • • Time: hours, minutes and seconds Twenty-four hour format (military time) Calendar: weekday, date, month and year Alarm configurable Year range: 2000 to 2099 Leap year correction BCD format for compact firmware Optimized for low-power operation User calibration with auto-adjust Calibration range: 2.64 seconds error per month Requirements: external 32.
PIC18F87K22 FAMILY 18.
PIC18F87K22 FAMILY 18.1.
PIC18F87K22 FAMILY REGISTER 18-2: RTCCAL: RTCC CALIBRATION REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown CAL<7:0>: RTC Drift Calibration bits 01111111 = Maximum positive adjustment. Adds 508 RTC clock pulses every minute. . . .
PIC18F87K22 FAMILY REGISTER 18-4: ALRMCFG: ALARM CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ALRMEN: Alarm Enable bit 1 = Alarm is enabled (cleared automatically after an alarm event whenever ARPT<7:0> = 00 and CHIME = 0) 0 = Al
PIC18F87K22 FAMILY REGISTER 18-5: ALRMRPT: ALARM REPEAT REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 18.1.2 x = Bit is unknown ARPT<7:0>: Alarm Repeat Counter Value bits 11111111 = Alarm will repeat 255 more times . . .
PIC18F87K22 FAMILY REGISTER 18-8: MONTH: MONTH VALUE REGISTER(1) U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit Contains a value of 0 or 1.
PIC18F87K22 FAMILY REGISTER 18-11: HOUR: HOUR VALUE REGISTER(1) U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit bits Contains a value from 0 to 2.
PIC18F87K22 FAMILY 18.1.
PIC18F87K22 FAMILY REGISTER 18-17: ALRMHR: ALARM HOURS VALUE REGISTER(1) U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit bits Contains a value from 0 to 2.
PIC18F87K22 FAMILY 18.1.4 RTCEN BIT WRITE 18.2 RTCWREN (RTCCFG<5>) must be set before a write to RTCEN can take place. Any write to the RTCEN bit, while RTCWREN = 0, will be ignored. Like the RTCEN bit, the RTCVALH and RTCVALL registers can only be written to when RTCWREN = 1. A write to these registers, while RTCWREN = 0, will be ignored. FIGURE 18-2: FIGURE 18-3: The register interface for the RTCC and alarm values is implemented using the Binary Coded Decimal (BCD) format.
PIC18F87K22 FAMILY 18.2.2 CLOCK SOURCE As previously mentioned, the RTCC module is intended to be clocked by an external Real-Time Clock (RTC) crystal, oscillating at 32.768 kHz, but an internal oscillator can be used. The RTCC clock selection is decided by the RTCOSC bit (CONFIG3L<0>). FIGURE 18-4: Calibration of the crystal can be done through this module to yield an error of 3 seconds or less per month. (For further details, see Section 18.2.9 “Calibration”.) CLOCK SOURCE MULTIPLEXING 32.
PIC18F87K22 FAMILY 18.2.4 LEAP YEAR Since the year range on the RTCC module is 2000 to 2099, the leap year calculation is determined by any year divisible by four in the above range. Only February is affected in a leap year. February will have 29 days in a leap year and 28 days in any other year. 18.2.5 GENERAL FUNCTIONALITY All Timer registers containing a time value of seconds or greater are writable.
PIC18F87K22 FAMILY TABLE 18-4: ALRMVAL REGISTER MAPPING Alarm Value Register Window ALRMPTR<1:0> 00 ALRMVALH ALRMVALL ALRMMIN ALRMSEC 01 ALRMWD ALRMHR 10 ALRMMNTH ALRMDAY 11 — — Writes to the RTCCAL register should occur only when the timer is turned off or immediately after the rising edge of the seconds pulse. Note: 18.3 In determining the crystal’s error value, it is the user’s responsibility to include the crystal’s initial error from drift due to temperature or crystal aging.
PIC18F87K22 FAMILY FIGURE 18-5: ALARM MASK SETTINGS Alarm Mask Setting AMASK<3:0> Day of the Week Month Day Hours Minutes Seconds 0000 – Every half second 0001 – Every second 0010 – Every 10 seconds s 0011 – Every minute s s m s s m m s s 0100 – Every 10 minutes 0101 – Every hour 0110 – Every day 0111 – Every week d 1000 – Every month 1001 – Every year(1) Note 1: m m h h m m s s h h m m s s d d h h m m s s d d h h m m s s Annually, except when configure
PIC18F87K22 FAMILY FIGURE 18-6: TIMER PULSE GENERATION RTCEN bit ALRMEN bit RTCC Alarm Event RTCC Pin 18.4 Sleep Mode The timer and alarm continue to operate while in Sleep mode. The operation of the alarm is not affected by Sleep, as an alarm event can always wake up the CPU. The Idle mode does not affect the operation of the timer or alarm. 18.5 18.5.1 Reset 18.5.2 POWER-ON RESET (POR) The RTCCFG and ALRMRPT registers are reset only on a POR.
PIC18F87K22 FAMILY 18.6 Register Maps Table 18-5, Table 18-6 and Table 18-7 summarize the registers associated with the RTCC module.
PIC18F87K22 FAMILY NOTES: DS39960D-page 244 2009-2011 Microchip Technology Inc.
PIC18F87K22 FAMILY 19.0 CAPTURE/COMPARE/PWM (CCP) MODULES PIC18F87K22 family devices have seven CCP (Capture/Compare/PWM) modules, designated CCP4 through CCP10. All the modules implement standard Capture, Compare and Pulse-Width Modulation (PWM) modes. Note: Each CCP module contains a 16-bit register that can operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register.
PIC18F87K22 FAMILY REGISTER 19-1: CCPxCON: CCPx CONTROL REGISTER (CCP4-CCP10 MODULES)(1) CCPxM<3:0>: CCPx Module Mode Select bits(2) 0000 = Capture/Compare/PWM disabled (resets CCPx module) 0001 = Reserved 0010 = Compare mode, toggle output on match (CCPxIF bit is set) 0011 = Reserved 0100 = Capture mode: every falling edge 0101 = Capture mode: every rising edge 0110 = Capture mode: every 4th rising edge 0111 = Capture mode: every 16th rising edge 1000 = Compare mode: initialize CCPx pin low; on compare m
PIC18F87K22 FAMILY REGISTER 19-3: CCPTMRS2: CCP TIMER SELECT REGISTER 2 U-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 — — — C10TSEL0(1) — C9TSEL0(1) C8TSEL1 C8TSEL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4 C10TSEL0: CCP10 Timer Selection bit(1) 0 = CCP10 is based off of TMR1/TMR2 1 = CCP10 is based off of TMR7/TMR2 bit 3 Unimplemented: Read
PIC18F87K22 FAMILY REGISTER 19-4: CCPRxL: CCPx PERIOD LOW BYTE REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x CCPRxL7 CCPRxL6 CCPRxL5 CCPRxL4 CCPRxL3 CCPRxL2 CCPRxL1 CCPRxL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown CCPRxL<7:0>: CCPx Period Register Low Byte bits Capture Mode: Capture Register Low Byte Compare Mode: Compare Register Low Byte
PIC18F87K22 FAMILY 19.1 TABLE 19-1: CCP Module Configuration Each Capture/Compare/PWM module is associated with a control register (generically, CCPxCON) and a data register (CCPRx). The data register, in turn, is comprised of two 8-bit registers: CCPRxL (low byte) and CCPRxH (high byte). All registers are both readable and writable. 19.1.1 CCP MODULES AND TIMER RESOURCES The CCP modules utilize Timers, 1 through 8, which vary with the selected mode.
PIC18F87K22 FAMILY 19.1.2 OPEN-DRAIN OUTPUT OPTION When operating in Output mode (the Compare or PWM modes), the drivers for the CCPx pins can be optionally configured as open-drain outputs. This feature allows the voltage level on the pin to be pulled to a higher level through an external pull-up resistor and allows the output to communicate with external circuits without the need for additional level shifters. The open-drain output option is controlled by the CCPxOD bits (ODCON2<7:0>).
PIC18F87K22 FAMILY FIGURE 19-1: CAPTURE MODE OPERATION BLOCK DIAGRAM TMR5H Set CCP5IF C5TSEL0 CCP5 Pin Prescaler 1, 4, 16 and Edge Detect CCP5CON<3:0> Q1:Q4 CCP4CON<3:0> 4 4 CCPR5L TMR1 Enable TMR1H TMR1L TMR3H TMR3L Set CCP4IF 4 C4TSEL1 C4TSEL0 TMR3 Enable CCP4 Pin Prescaler 1, 4, 16 TMR5 Enable CCPR5H C5TSEL0 TMR5L and Edge Detect CCPR4H CCPR4L TMR1 Enable C4TSEL0 C4TSEL1 Note: 19.2.3 TMR1L This block diagram uses CCP4 and CCP5, and their appropriate timers as an example.
PIC18F87K22 FAMILY 19.3 Compare Mode 19.3.3 SOFTWARE INTERRUPT MODE In Compare mode, the 16-bit CCPR4 register value is constantly compared against the Timer register pair value selected in the CCPTMR1 register. When a match occurs, the CCP4 pin can be: When the Generate Software Interrupt mode is chosen (CCP4M<3:0> = 1010), the CCP4 pin is not affected. Only a CCP interrupt is generated, if enabled, and the CCP4IE bit is set. • • • • 19.3.
PIC18F87K22 FAMILY FIGURE 19-2: COMPARE MODE OPERATION BLOCK DIAGRAM CCPR5H Set CCP5IF CCPR5L Special Event Trigger (Timer1/5 Reset) CCP5 Pin S Output Logic Compare Match Comparator Q R TRIS Output Enable 4 CCP5CON<3:0> TMR1H TMR1L 0 TMR5H TMR5L 1 C5TSEL0 0 TMR1H TMR1L 1 TMR5H TMR5L Special Event Trigger (Timer1/Timer3 Reset, A/D Trigger) C4TSEL1 C4TSEL0 Set CCP4IF Comparator CCPR4H Compare Match CCP4 Pin Output Logic S Q R TRIS Output Enable 4 CCPR4L CCP4CON<3:0> Note:
PIC18F87K22 FAMILY TABLE 19-5: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1/3/5/7 (CONTINUED) Name TMR1H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Timer1 Register High Byte TMR3L Timer3 Register Low Byte TMR3H Timer3 Register High Byte TMR5L Timer5 Register Low Byte TMR5H Timer5 Register High Byte TMR7L(1) Timer7 Register Low Byte TMR7H(1) Timer7 Register High Byte T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 SOSCEN T1SYNC RD16 TMR1ON T3CON TMR3CS1 TMR3CS0 T3CKPS1 T3C
PIC18F87K22 FAMILY 19.4 PWM Mode In Pulse-Width Modulation (PWM) mode, the CCP4 pin produces up to a 10-bit resolution PWM output. Since the CCP4 pin is multiplexed with a PORTC or PORTE data latch, the appropriate TRIS bit must be cleared to make the CCP4 pin an output. A PWM output (Figure 19-4) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period).
PIC18F87K22 FAMILY 19.4.2 PWM DUTY CYCLE The CCPR4H register and a two-bit internal latch are used to double-buffer the PWM duty cycle. This double-buffering is essential for glitchless PWM operation. The PWM duty cycle is specified to use CCP4, as an example, by writing to the CCPR4L register and to the CCP4CON<5:4> bits. Up to 10-bit resolution is available. The CCPR4L contains the eight MSbs and the CCP4CON<5:4> bits contain the two LSbs. This 10-bit value is represented by CCPR4L:CCP4CON<5:4>.
PIC18F87K22 FAMILY TABLE 19-7: Name (2) TRISH REGISTERS ASSOCIATED WITH PWM AND TIMERS (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 TMR2 Timer2 Register TMR4 Timer4 Register TMR6 Timer6 Register TMR8 Timer8 Register PR2 Timer2 Period Register PR4 Timer4 Period Register PR6 Timer6 Period Register PR8 Timer8 Period Register T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 T4CON —
PIC18F87K22 FAMILY NOTES: DS39960D-page 258 2009-2011 Microchip Technology Inc.
PIC18F87K22 FAMILY 20.0 ENHANCED CAPTURE/COMPARE/PWM (ECCP) MODULE PIC18F87K22 family devices have three Enhanced Capture/Compare/PWM (ECCP) modules: ECCP1, ECCP2 and ECCP3. These modules contain a 16-bit register, which can operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register. These ECCP modules are upward compatible with CCP.
PIC18F87K22 FAMILY REGISTER 20-1: CCPxCON: ENHANCED CAPTURE/COMPARE/PWMx CONTROL R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PxM1 PxM0 DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 PxM<1:0>: Enhanced PWM Output Configuration bits If CCPxM<3:2> = 00, 01, 10: xx = PxA is assigned as capture/compare input/output; Px
PIC18F87K22 FAMILY REGISTER 20-2: CCPTMRS0: CCP TIMER SELECT 0 REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 C3TSEL1 C3TSEL0 C2TSEL2 C2TSEL1 C2TSEL0 C1TSEL2 C1TSEL1 C1TSEL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 C3TSEL<1:0>: ECCP3 Timer Selection bits 00 = ECCP3 is based off of TMR1/TMR2 01 = ECCP3 is based off of TMR3/TMR4 10 = ECCP3 is
PIC18F87K22 FAMILY In addition to the expanded range of modes available through the CCPxCON and ECCPxAS registers, the ECCP modules have two additional registers associated with Enhanced PWM operation and auto-shutdown features. They are: • ECCPxDEL – Enhanced PWM Control • PSTRxCON – Pulse Steering Control 20.1 ECCP Outputs and Configuration The Enhanced CCP module may have up to four PWM outputs, depending on the selected operating mode.
PIC18F87K22 FAMILY 20.2 20.2.2 Capture Mode In Capture mode, the CCPRxH:CCPRxL register pair captures the 16-bit value of the TMR1 or TMR3 registers when an event occurs on the corresponding ECCPx pin. An event is defined as one of the following: • • • • Every falling edge Every rising edge Every fourth rising edge Every 16th rising edge TABLE 20-2: ECCP1/2/3 INTERRUPT FLAG BITS ECCP Module Flag Bit 1 PIR3<1> 2 PIR3<2> 3 PIR4<0> 20.2.
PIC18F87K22 FAMILY 20.3 20.3.2 Compare Mode In Compare mode, the 16-bit CCPRx register value is constantly compared against the Timer register pair value selected in the CCPTMR1 register. When a match occurs, the ECCPx pin can be: • • • • Driven high Driven low Toggled (high-to-low or low-to-high) Unchanged (that is, reflecting the state of the I/O latch) The action on the pin is based on the value of the mode select bits (CCPxM<3:0>). At the same time, the interrupt flag bit, CCPxIF, is set. 20.3.
PIC18F87K22 FAMILY 20.4 The PWM outputs are multiplexed with I/O pins and are designated: PxA, PxB, PxC and PxD. The polarity of the PWM pins is configurable and is selected by setting the CCPxM bits in the CCPxCON register appropriately. PWM (Enhanced Mode) The Enhanced PWM mode can generate a PWM signal on up to four different output pins with up to 10 bits of resolution. It can do this through four different PWM Output modes: • • • • Table 20-1 provides the pin assignments for each Enhanced PWM mode.
PIC18F87K22 FAMILY TABLE 20-3: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES ECCP Mode PxM<1:0> PxA PxB PxC PxD Single 00 Yes(1) Yes(1) Yes(1) Yes(1) Half-Bridge 10 Yes Yes No No Full-Bridge, Forward 01 Yes Yes Yes Yes Full-Bridge, Reverse 11 Yes Yes Yes Yes Note 1: Outputs are enabled by pulse steering in Single mode (see Register 20-5).
PIC18F87K22 FAMILY FIGURE 20-5: EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) PxM<1:0> Signal PR2 + 1 Pulse Width 0 Period 00 (Single Output) PxA Modulated PxA Modulated 10 (Half-Bridge) Delay(1) Delay(1) PxB Modulated PxA Active 01 (Full-Bridge, Forward) PxB Inactive PxC Inactive PxD Modulated PxA Inactive 11 (Full-Bridge, Reverse) PxB Modulated PxC Active PxD Inactive Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Pulse Width = TOSC * (CCPRxL<7
PIC18F87K22 FAMILY 20.4.1 HALF-BRIDGE MODE In Half-Bridge mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the PxA pin, while the complementary PWM output signal is output on the PxB pin (see Figure 20-6). This mode can be used for half-bridge applications, as shown in Figure 20-7, or for full-bridge applications, where four power switches are being modulated with two PWM signals.
PIC18F87K22 FAMILY 20.4.2 FULL-BRIDGE MODE In the Reverse mode, the PxC pin is driven to its active state and the PxB pin is modulated, while the PxA and PxD pins are driven to their inactive state, as provided Figure 20-9. In Full-Bridge mode, all four pins are used as outputs. An example of a full-bridge application is provided in Figure 20-8. The PxA, PxB, PxC and PxD outputs are multiplexed with the port data latches.
PIC18F87K22 FAMILY FIGURE 20-9: EXAMPLE OF FULL-BRIDGE PWM OUTPUT Forward Mode Period PxA (2) Pulse Width PxB(2) PxC(2) PxD(2) (1) (1) Reverse Mode Period Pulse Width PxA(2) PxB(2) PxC(2) PxD(2) (1) Note 1: 2: (1) At this time, the TMR2 register is equal to the PR2 register. The output signal is shown as active-high. DS39960D-page 270 2009-2011 Microchip Technology Inc.
PIC18F87K22 FAMILY 20.4.2.1 Direction Change in Full-Bridge Mode In Full-Bridge mode, the PxM1 bit in the CCPxCON register allows users to control the forward/reverse direction. When the application firmware changes this direction control bit, the module will change to the new direction on the next PWM cycle. A direction change is initiated in software by changing the PxM1 bit of the CCPxCON register.
PIC18F87K22 FAMILY FIGURE 20-11: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE(1) Forward Period t1 Reverse Period PxA PxB PW PxC PxD PW TON(2) External Switch C TOFF(3) External Switch D Potential Shoot-Through Current Note 1: 20.4.3 All signals are shown as active-high. 2: TON is the turn-on delay of power switch, QC, and its driver. 3: TOFF is the turn-off delay of power switch, QD, and its driver.
PIC18F87K22 FAMILY When a shutdown event occurs, two things happen: Each pin pair may be placed into one of three states: • The ECCPxASE bit is set to ‘1’. The ECCPxASE will remain set until cleared in firmware or an auto-restart occurs. (See Section 20.4.5 “Auto-Restart Mode”.) • The enabled PWM pins are asynchronously placed in their shutdown states. The PWM output pins are grouped into pairs (PxA/PxC) and (PxB/PxD).
PIC18F87K22 FAMILY FIGURE 20-12: PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PxRSEN = 0) PWM Period Shutdown Event ECCPxASE bit PWM Activity Normal PWM Shutdown Event Occurs Start of PWM Period 20.4.5 AUTO-RESTART MODE The Enhanced PWM can be configured to automatically restart the PWM signal once the auto-shutdown condition has been removed. Auto-restart is enabled by setting the PxRSEN bit (ECCPxDEL<7>).
PIC18F87K22 FAMILY 20.4.6 PROGRAMMABLE DEAD-BAND DELAY MODE FIGURE 20-14: In half-bridge applications, where all power switches are modulated at the PWM frequency, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on and the other turned off), both switches may be on for a short period until one switch completely turns off.
PIC18F87K22 FAMILY REGISTER 20-4: ECCPxDEL: ENHANCED PWM CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PxRSEN PxDC6 PxDC5 PxDC4 PxDC3 PxDC2 PxDC1 PxDC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PxRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCPxASE bit clears automatically once the shutdown event goes away; the PWM restart
PIC18F87K22 FAMILY REGISTER 20-5: R/W-0 CMPL1 PSTRxCON: PULSE STEERING CONTROL(1) R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 CMPL0 — STRSYNC STRD STRC STRB STRA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 CMPL<1:0>: Complementary Mode Output Assignment Steering Sync bits 00 = See STR 01 = PA and PB are selected as the complementary output pair 10 = PA and
PIC18F87K22 FAMILY FIGURE 20-16: 20.4.7.1 SIMPLIFIED STEERING BLOCK DIAGRAM The STRSYNC bit of the PSTRxCON register gives the user two choices for when the steering event will happen. When the STRSYNC bit is ‘0’, the steering event will happen at the end of the instruction that writes to the PSTRxCON register. In this case, the output signal at the Px pins may be an incomplete PWM waveform. This operation is useful when the user firmware needs to immediately remove a PWM signal from the pin.
PIC18F87K22 FAMILY 20.4.8 OPERATION IN POWER-MANAGED MODES 20.4.8.1 Operation with Fail-Safe Clock Monitor (FSCM) In Sleep mode, all clock sources are disabled. Timer2/4/6/8 will not increment and the state of the module will not change. If the ECCPx pin is driving a value, it will continue to drive that value. When the device wakes up, it will continue from this state. If Two-Speed Start-ups are enabled, the initial start-up frequency from HF-INTOSC and the postscaler may not be immediately stable.
PIC18F87K22 FAMILY TABLE 20-4: File Name T1CON REGISTERS ASSOCIATED WITH ECCP1/2/3 MODULE AND TIMER1/2/3/4/6/8/10/12 (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 SOSCEN T1SYNC RD16 TMR1ON T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 T3CON TMR3CS1 TMR3CS0 T3CKPS1 T3CKPS0 SOSCEN T3SYNC RD16 TMR3ON T4CON — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 T6CON — T6OUTPS3 T6OUTPS2 T6OUT
PIC18F87K22 FAMILY 21.0 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE 21.1 Master SSP (MSSP) Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D Converters, etc.
PIC18F87K22 FAMILY 21.3.1 REGISTERS Each MSSP module has four registers for SPI mode operation. These are: • MSSPx Control Register 1 (SSPxCON1) • MSSPx Status Register (SSPxSTAT) • Serial Receive/Transmit Buffer Register (SSPxBUF) • MSSPx Shift Register (SSPxSR) – Not directly accessible SSPxSR is the shift register used for shifting data in or out. SSPxBUF is the buffer register to which data bytes are written to or read from.
PIC18F87K22 FAMILY REGISTER 21-2: SSPxCON1: MSSPx CONTROL REGISTER 1 (SPI MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV(1) SSPEN(2) CKP SSPM3(3) SSPM2(3) SSPM1(3) SSPM0(3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit 1 = The SSPxBUF register is written while it is still transmitting the previous word (must
PIC18F87K22 FAMILY 21.3.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>).
PIC18F87K22 FAMILY 21.3.4 ENABLING SPI I/O To enable the serial port, MSSP Enable bit, SSPEN (SSPxCON1<5>), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, re-initialize the SSPxCON registers and then set the SSPEN bit. This configures the SDIx, SDOx, SCKx and SSx pins as serial port pins.
PIC18F87K22 FAMILY 21.3.6 MASTER MODE The master can initiate the data transfer at any time because it controls the SCKx. The master determines when the slave (Processor 1, Figure 21-2) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPxBUF register is written to. If the SPI is only going to receive, the SDOx output could be disabled (programmed as an input).
PIC18F87K22 FAMILY 21.3.7 SLAVE MODE In Slave mode, the data is transmitted and received as the external clock pulses appear on SCKx. When the last bit is latched, the SSPxIF interrupt flag bit is set. While in Slave mode, the external clock is supplied by the external clock source on the SCKx pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. While in Sleep mode, the slave can transmit/receive data.
PIC18F87K22 FAMILY FIGURE 21-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SSx Optional SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF SDOx SDIx (SMP = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 bit 7 Input Sample (SMP = 0) SSPxIF Interrupt Flag Next Q4 Cycle after Q2 SSPxSR to SSPxBUF FIGURE 21-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SSx Not Optional SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 1) Write to SSPxBUF SDOx SDIx (SMP = 0) bit 7 bit 7 bit
PIC18F87K22 FAMILY 21.3.9 OPERATION IN POWER-MANAGED MODES In SPI Master mode, module clocks may be operating at a different speed than when in Full-Power mode. In the case of Sleep mode, all clocks are halted. 21.3.11 BUS MODE COMPATIBILITY Table 21-1 shows the compatibility between the standard SPI modes and the states of the CKP and CKE control bits. In Idle modes, a clock is provided to the peripherals.
PIC18F87K22 FAMILY TABLE 21-2: Name INTCON REGISTERS ASSOCIATED WITH SPI OPERATION Bit 7 Bit 6 GIE/GIEH PEIE/GIEL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF PIR2 OSCFIF — SSP2IF BCL2IF BCL1IF HLVDIF TMR3IF TMR3GIF PIE2 OSCFIE — SSP2IE BCL2IE BCL1IE HLVDIE TMR3IE TMR3GIE IPR2 OSCFIP — SSP2IP BCL2IP BCL1IP HLVDIP TMR3IP TMR3GIP PIR3 TMR5GIF — RC2IF TX2IF CTMUIF CCP2IF CCP1IF RTCCIF PIE3 TMR5GIE — RC2IE TX2IE CTMUIE CCP2IE
PIC18F87K22 FAMILY 21.4 I2C Mode 21.4.1 The MSSP module in I 2C mode fully implements all master and slave functions (including general call support), and provides interrupts on Start and Stop bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing.
PIC18F87K22 FAMILY REGISTER 21-3: R/W-0 SSPxSTAT: MSSPx STATUS REGISTER (I2C™ MODE) R/W-0 SMP CKE R-0 R-0 R-0 D/A (1) (1) P S R-0 R/W (2,3) R-0 R-0 UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control is disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control is enab
PIC18F87K22 FAMILY REGISTER 21-4: R/W-0 SSPxCON1: MSSPx CONTROL REGISTER 1 (I2C™ MODE) R/W-0 WCOL SSPOV R/W-0 SSPEN (1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CKP SSPM3(2) SSPM2(2) SSPM1(2) SSPM0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPxBUF register was attempted while the I2C con
PIC18F87K22 FAMILY REGISTER 21-5: SSPxCON2: MSSPx CONTROL REGISTER 2 (I2C™ MASTER MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT(1) ACKEN(2) RCEN(2) PEN(2) RSEN(2) SEN(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GCEN: General Call Enable bit Unused in Master mode.
PIC18F87K22 FAMILY REGISTER 21-6: SSPxCON2: MSSPx CONTROL REGISTER 2 (I2C™ SLAVE MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT(1) ACKEN(1) RCEN(1) PEN(1) RSEN(1) SEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GCEN: General Call Enable bit 1 = Enables interrupt when a general call address (0000h) is received in the SSPxSR 0 =
PIC18F87K22 FAMILY 21.4.2 OPERATION The MSSP module functions are enabled by setting the MSSP Enable bit, SSPEN (SSPxCON1<5>). The SSPxCON1 register allows control of the I2C operation.
PIC18F87K22 FAMILY 21.4.3.2 Address Masking Modes Masking an address bit causes that bit to become a “don’t care”. When one address bit is masked, two addresses will be Acknowledged and cause an interrupt. It is possible to mask more than one address bit at a time, which greatly expands the number of addresses Acknowledged. The I2C slave behaves the same way whether address masking is used or not. However, when address masking is used, the I2C slave can Acknowledge multiple addresses and cause interrupts.
PIC18F87K22 FAMILY 21.4.3.4 7-Bit Address Masking Mode Unlike 5-bit masking, 7-Bit Address Masking mode uses a mask of up to 8 bits (in 10-bit addressing) to define a range of addresses that can be Acknowledged, using the lowest bits of the incoming address. This allows the module to Acknowledge up to 127 different addresses with 7-bit addressing, or 255 with 10-bit addressing (see Example 21-3). This mode is the default configuration of the module, which is selected when MSSPMSK is unprogrammed (‘1’).
PIC18F87K22 FAMILY 21.4.3.5 Reception When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPxSTAT register is cleared. The received address is loaded into the SSPxBUF register and the SDAx line is held low (ACK). When the address byte overflow condition exists, then the no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit, BF (SSPxSTAT<0>), is set or bit, SSPOV (SSPxCON1<6>), is set.
DS39960D-page 300 2 A6 3 4 A4 5 A3 Receiving Address A5 6 A2 (CKP does not reset to ‘0’ when SEN = 0) CKP (SSPxCON<4>) SSPOV (SSPxCON1<6>) BF (SSPxSTAT<0>) SSPxIF (PIR1<3> or PIR3<7>) 1 SCLx S A7 7 A1 8 9 ACK R/W = 0 1 D7 3 4 D4 5 D3 Receiving Data D5 Cleared in software SSPxBUF is read 2 D6 6 D2 7 D1 8 D0 9 ACK 1 D7 2 D6 3 4 D4 5 D3 Receiving Data D5 6 D2 7 D1 8 D0 Bus master terminates transfer P SSPOV is set because SSPxBUF is still full.
2009-2011 Microchip Technology Inc. 2 A6 Note 3 A5 4 X 5 A3 6 X 1 3 4 D4 Cleared in software SSPxBUF is read 2 D5 5 D3 6 D2 7 D1 8 D0 In this example, an address equal to A7.A6.A5.X.A3.X.X will be Acknowledged and cause an interrupt. 9 D6 x = Don’t care (i.e., address bit can either be a ‘1’ or a ‘0’).
DS39960D-page 302 2 Data in sampled 1 A6 CKP (SSPxCON<4>) BF (SSPxSTAT<0>) SSPxIF (PIR1<3> or PIR3<7>) S A7 3 4 A4 5 A3 6 A2 Receiving Address A5 7 A1 8 R/W = 1 9 ACK 3 D5 4 5 D3 SSPxBUF is written in software 6 D2 Transmitting Data D4 Cleared in software 2 D6 CKP is set in software Clear by reading SCLx held low while CPU responds to SSPxIF 1 D7 7 8 D0 9 From SSPxIF ISR D1 ACK 1 D7 4 D4 5 D3 Cleared in software 3 D5 6 D2 CKP is set in software SS
2009-2011 Microchip Technology Inc. 2 1 3 1 5 0 7 A8 8 UA is set indicating that the SSPxADD needs to be updated SSPxBUF is written with contents of SSPxSR 6 A9 9 2 X 4 5 A3 6 A2 4 5 6 Cleared in software 3 7 8 9 1 2 4 5 6 Cleared in software 3 D3 D2 Receive Data Byte D1 D0 ACK D7 D6 D5 D4 Cleared by hardware when SSPxADD is updated with high byte of address 2 D3 D2 Note that the Most Significant bits of the address are not affected by the bit masking.
DS39960D-page 304 2 1 3 1 4 1 5 0 7 A8 8 UA is set indicating that the SSPxADD needs to be updated SSPxBUF is written with contents of SSPxSR 6 A9 9 (CKP does not reset to ‘0’ when SEN = 0) CKP (SSPxCON<4>) UA (SSPxSTAT<1>) SSPOV (SSPxCON1<6>) BF (SSPxSTAT<0>) Cleared in software SSPxIF (PIR1<3> or PIR3<7>) 1 SCLx S 1 ACK R/W = 0 A7 2 4 A4 5 A3 6 A2 8 9 A0 ACK UA is set indicating that SSPxADD needs to be updated Cleared by hardware when SSPxADD is updated with low b
2009-2011 Microchip Technology Inc.
PIC18F87K22 FAMILY 21.4.4 CLOCK STRETCHING If the user polls the UA bit and clears it by updating the SSPxADD register before the falling edge of the ninth clock occurs, and if the user hasn’t cleared the BF bit by reading the SSPxBUF register before that time, then the CKP bit will still NOT be asserted low. Clock stretching, on the basis of the state of the BF bit, only occurs during a data sequence, not an address sequence.
PIC18F87K22 FAMILY 21.4.4.5 Clock Synchronization and the CKP bit When the CKP bit is cleared, the SCLx output is forced to ‘0’. However, clearing the CKP bit will not assert the SCLx output low until the SCLx output is already sampled low. Therefore, the CKP bit will not assert the SCLx line until an external I2C master device has FIGURE 21-14: already asserted the SCLx line. The SCLx output will remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCLx.
DS39960D-page 308 2 A6 CKP (SSPxCON<4>) SSPOV (SSPxCON1<6>) BF (SSPxSTAT<0>) SSPxIF (PIR1<3> or PIR3<7>) 1 SCLx S A7 3 4 A4 5 A3 6 A2 Receiving Address A5 7 A1 8 9 ACK R/W = 0 3 4 D4 5 D3 Receiving Data D5 Cleared in software 2 D6 If BF is cleared prior to the falling edge of the 9th clock, CKP will not be reset to ‘0’ and no clock stretching will occur SSPxBUF is read 1 D7 6 D2 7 D1 9 ACK 1 D7 BF is set after falling edge of the 9th clock, CKP is reset to ‘0’ a
2009-2011 Microchip Technology Inc.
PIC18F87K22 FAMILY 21.4.5 GENERAL CALL ADDRESS SUPPORT If the general call address matches, the SSPxSR is transferred to the SSPxBUF, the BF flag bit is set (eighth bit), and on the falling edge of the ninth bit (ACK bit), the SSPxIF interrupt flag bit is set. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master. The exception is the general call address which can address all devices.
PIC18F87K22 FAMILY MASTER MODE Note: Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPxCON1, and by setting the SSPEN bit. In Master mode, the SCLx and SDAx lines are manipulated by the MSSP hardware if the TRIS bits are set. The Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled.
PIC18F87K22 FAMILY 21.4.6.1 I2C™ Master Mode Operation The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDAx while SCLx outputs the serial clock.
PIC18F87K22 FAMILY 21.4.7 BAUD RATE 21.4.7.1 2 In I C Master mode, the Baud Rate Generator (BRG) reload value is placed in the lower 7 bits of the SSPxADD register (Figure 21-19). When a write occurs to SSPxBUF, the Baud Rate Generator will automatically begin counting. The BRG counts down to 0 and stops until another reload has taken place. The BRG count is decremented twice per instruction cycle (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the BRG is reloaded automatically.
PIC18F87K22 FAMILY 21.4.7.2 Clock Arbitration Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, deasserts the SCLx pin (SCLx allowed to float high). When the SCLx pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCLx pin is actually sampled high. When the FIGURE 21-20: SDAx SCLx pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<6:0> and begins counting.
PIC18F87K22 FAMILY 21.4.8 I2C™ MASTER MODE START CONDITION TIMING Note: To initiate a Start condition, the user sets the Start Enable bit, SEN (SSPxCON2<0>). If the SDAx and SCLx pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<6:0> and starts its count. If SCLx and SDAx are both sampled high when the Baud Rate Generator times out (TBRG), the SDAx pin is driven low.
PIC18F87K22 FAMILY 21.4.9 I2C™ MASTER MODE REPEATED START CONDITION TIMING Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. A Repeated Start condition occurs when the RSEN bit (SSPxCON2<1>) is programmed high and the I2C logic module is in the Idle state. When the RSEN bit is set, the SCLx pin is asserted low. When the SCLx pin is sampled low, the Baud Rate Generator is loaded with the contents of SSPxADD<5:0> and begins counting.
PIC18F87K22 FAMILY 21.4.10 I2C™ MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address or the other half of a 10-bit address, is accomplished by simply writing a value to the SSPxBUF register. This action will set the Buffer Full flag bit, BF, and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDAx pin after the falling edge of SCLx is asserted (see data hold time specification Parameter 106).
DS39960D-page 318 S R/W PEN SEN BF (SSPxSTAT<0>) SSPxIF SCLx SDAx A6 A5 A4 A3 A2 A1 3 4 5 Cleared in software 2 6 7 8 After Start condition, SEN cleared by hardware SSPxBUF written 1 9 D7 1 SCLx held low while CPU responds to SSPxIF ACK = 0 R/W = 0 SSPxBUF written with 7-bit address and R/W, start transmit A7 Transmit Address to Slave 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 SSPxBUF is written in software Cleared in software service routine from MSSP interrupt 2 D6 Trans
2009-2011 Microchip Technology Inc.
PIC18F87K22 FAMILY 21.4.12 ACKNOWLEDGE SEQUENCE TIMING 21.4.13 A Stop bit is asserted on the SDAx pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN (SSPxCON2<2>). At the end of a receive/transmit, the SCLx line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDAx line low. When the SDAx line is sampled low, the Baud Rate Generator is reloaded and counts down to 0.
PIC18F87K22 FAMILY 21.4.14 SLEEP OPERATION 21.4.17 2 While in Sleep mode, the I C module can receive addresses or data, and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled). 21.4.15 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. 21.4.
PIC18F87K22 FAMILY 21.4.17.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDAx or SCLx is sampled low at the beginning of the Start condition (Figure 21-28). SCLx is sampled low before SDAx is asserted low (Figure 21-29). During a Start condition, both the SDAx and the SCLx pins are monitored. If the SDAx pin is sampled low during this count, the BRG is reset and the SDAx line is asserted early (Figure 21-30).
PIC18F87K22 FAMILY FIGURE 21-29: BUS COLLISION DURING START CONDITION (SCLx = 0) SDAx = 0, SCLx = 1 TBRG TBRG SDAx Set SEN, Enable Start Sequence if SDAx = 1, SCLx = 1 SCLx SCLx = 0 Before SDAx = 0, Bus Collision Occurs, Set BCLxIF SEN SCLx = 0 Before BRG Time-out, Bus Collision Occurs, Set BCLxIF BCLxIF Interrupt Cleared in Software S ‘0’ ‘0’ SSPxIF ‘0’ ‘0’ FIGURE 21-30: BRG RESET DUE TO SDAx ARBITRATION DURING START CONDITION SDAx = 0, SCLx = 1 Set S Less than TBRG SDAx Set SSPxIF TBRG S
PIC18F87K22 FAMILY 21.4.17.2 Bus Collision During a Repeated Start Condition If SDAx is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ‘0’, Figure 21-31). If SDAx is sampled high, the BRG is reloaded and begins counting. If SDAx goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDAx at exactly the same time.
PIC18F87K22 FAMILY 21.4.17.3 Bus Collision During a Stop Condition The Stop condition begins with SDAx asserted low. When SDAx is sampled low, the SCLx pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPxADD<6:0> and counts down to 0. After the BRG times out, SDAx is sampled. If SDAx is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ‘0’ (Figure 21-33).
PIC18F87K22 FAMILY TABLE 21-4: REGISTERS ASSOCIATED WITH I2C™ OPERATION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF TMR1GIF TMR2IF TMR1IF PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE TMR1GIE TMR2IE TMR1IE IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP TMR1GIP TMR2IP TMR1IP INTCON PIR2 OSCFIF — SSP2IF BLC2IF BCL1IF HLVDIF TMR3IF TMR3GIF PIE2 OSCFIE — SSP2IE BLC2IE BCL1IE
PIC18F87K22 FAMILY 22.0 ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART) The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is one of two serial I/O modules. (Generically, the EUSART is also known as a Serial Communications Interface or SCI.) The EUSART can be configured as a full-duplex, asynchronous system that can communicate with peripheral devices, such as CRT terminals and personal computers.
PIC18F87K22 FAMILY REGISTER 22-1: TXSTAx: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care.
PIC18F87K22 FAMILY REGISTER 22-2: RCSTAx: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port is enabled 0 = Serial port is disabled (held in Reset) bit 6 RX9: 9-Bit Receive Enable bit 1 = Selects 9-bi
PIC18F87K22 FAMILY REGISTER 22-3: BAUDCONx: BAUD RATE CONTROL REGISTER R/W-0 R-1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ABDOVF: Auto-Baud Acquisition Rollover Status bit 1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software) 0 = No BRG
PIC18F87K22 FAMILY 22.1 Baud Rate Generator (BRG) The BRG is a dedicated, 8-bit or 16-bit generator that supports both the Asynchronous and Synchronous modes of the EUSART. By default, the BRG operates in 8-bit mode; setting the BRG16 bit (BAUDCONx<3>) selects 16-bit mode. The SPBRGHx:SPBRGx register pair controls the period of a free-running timer. In Asynchronous mode, bits, BRGH (TXSTAx<2>) and BRG16 (BAUDCONx<3>), also control the baud rate. In Synchronous mode, BRGH is ignored.
PIC18F87K22 FAMILY EXAMPLE 22-1: CALCULATING BAUD RATE ERROR For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, and 8-bit BRG: Desired Baud Rate = FOSC/(64 ([SPBRGHx:SPBRGx] + 1)) Solving for SPBRGHx:SPBRGx: X = ((FOSC/Desired Baud Rate)/64) – 1 = ((16000000/9600)/64) – 1 = [25.042] = 25 Calculated Baud Rate = 16000000/(64 (25 + 1)) = 9615 Error = (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate = (9615 – 9600)/9600 = 0.
PIC18F87K22 FAMILY TABLE 22-3: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE (K) FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz (decimal) % Error — — — — — 1.221 2.441 1.73 255 9.615 0.16 64 19.531 1.73 31 57.6 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2 — — — 115.2 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1 — — — % Error 0.3 1.2 — — 2.4 9.6 19.2 SPBRG value (decimal) Actual Rate (K) % Error — 1.73 — 255 — 1.
PIC18F87K22 FAMILY TABLE 22-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE (K) FOSC = 40.000 MHz Actual Rate (K) % Error FOSC = 20.000 MHz SPBRG value (decimal) Actual Rate (K) % Error FOSC = 10.000 MHz (decimal) Actual Rate (K) SPBRG value % Error FOSC = 8.000 MHz (decimal) Actual Rate (K) % Error SPBRG value SPBRG value (decimal) 0.3 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082 0.300 -0.04 1.2 1.200 0.02 2082 1.200 -0.
PIC18F87K22 FAMILY 22.1.3 AUTO-BAUD RATE DETECT The Enhanced USART module supports the automatic detection and calibration of baud rate. This feature is active only in Asynchronous mode and while the WUE bit is clear. Note 1: If the WUE bit is set with the ABDEN bit, Auto-Baud Rate Detection will occur on the byte following the Break character. 2: It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG clock source.
PIC18F87K22 FAMILY FIGURE 22-1: BRG Value AUTOMATIC BAUD RATE CALCULATION XXXXh RXx Pin 0000h 001Ch Start Edge #1 Bit 1 Bit 0 Edge #2 Bit 3 Bit 2 Edge #3 Bit 5 Bit 4 Edge #4 Bit 7 Bit 6 Edge #5 Stop Bit BRG Clock Auto-Cleared Set by User ABDEN bit RCxIF bit (Interrupt) Read RCREGx SPBRGx XXXXh 1Ch SPBRGHx XXXXh 00h Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.
PIC18F87K22 FAMILY 22.2 EUSART Asynchronous Mode The Asynchronous mode of operation is selected by clearing the SYNC bit (TXSTAx<4>). In this mode, the EUSART uses standard Non-Return-to-Zero (NRZ) format (one Start bit, eight or nine data bits and one Stop bit). The most common data format is 8 bits. An on-chip, dedicated 8-bit/16-bit Baud Rate Generator can be used to derive standard baud rate frequencies from the oscillator. The EUSART transmits and receives the LSb first.
PIC18F87K22 FAMILY FIGURE 22-3: EUSART TRANSMIT BLOCK DIAGRAM Data Bus TXxIF TXREGx Register TXxIE 8 MSb LSb (8) Pin Buffer and Control 0 TSR Register TXx Pin Interrupt TXEN Baud Rate CLK TRMT BRG16 SPBRGHx SPBRGx TX9 Baud Rate Generator FIGURE 22-4: Write to TXREGx BRG Output (Shift Clock) Word 1 Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXxIF bit (Transmit Buffer Reg. Empty Flag) FIGURE 22-5: TX9D ASYNCHRONOUS TRANSMISSION TXx (pin) TRMT bit (Transmit Shift Reg.
PIC18F87K22 FAMILY TABLE 22-5: Name REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF TMR1GIF TMR2IF TMR1IF PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE TMR1GIE TMR2IE TMR1IE IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP TMR1GIP TMR2IP TMR1IP INTCON PIR3 TMR5GIF — RC2IF TX2IF CTMUIF CCP2IF CCP1IF RTCCIF PIE3 TMR5GIE — RC2IE TX2IE
PIC18F87K22 FAMILY 22.2.2 EUSART ASYNCHRONOUS RECEIVER 22.2.3 The receiver block diagram is shown in Figure 22-6. The data is received on the RXx pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. This mode would typically be used in RS-232 systems. This mode would typically be used in RS-485 systems.
PIC18F87K22 FAMILY FIGURE 22-7: ASYNCHRONOUS RECEPTION Start bit RXx (pin) bit 0 bit 1 bit 7/8 Stop bit Rcv Shift Reg Rcv Buffer Reg Start bit bit 0 bit 7/8 Start bit bit 7/8 Stop bit Word 2 RCREGx Word 1 RCREGx Read Rcv Buffer Reg RCREGx Stop bit RCxIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RXx input. The RCREGx (Receive Buffer) is read after the third word, causing the OERR (Overrun) bit to be set.
PIC18F87K22 FAMILY 22.2.4 AUTO-WAKE-UP ON SYNC BREAK CHARACTER During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator is inactive and a proper byte reception cannot be performed. The auto-wake-up feature allows the controller to wake up due to activity on the RXx/DTx line while the EUSART is operating in Asynchronous mode. The auto-wake-up feature is enabled by setting the WUE bit (BAUDCONx<1>).
PIC18F87K22 FAMILY 22.2.4.2 Special Considerations Using the WUE Bit The timing of WUE and RCxIF events may cause some confusion when it comes to determining the validity of received data. As noted, setting the WUE bit places the EUSART in an Idle mode. The wake-up event causes a receive interrupt by setting the RCxIF bit. The WUE bit is cleared after this when a rising edge is seen on RXx/DTx. The interrupt condition is then cleared by reading the RCREGx register.
PIC18F87K22 FAMILY 22.2.5 BREAK CHARACTER SEQUENCE The EUSART module has the capability of sending the special Break character sequences that are required by the LIN/J2602 bus standard. The Break character transmit consists of a Start bit, followed by twelve ‘0’ bits and a Stop bit. The Frame Break character is sent whenever the SENDB and TXEN bits (TXSTAx<3> and TXSTAx<5>, respectively) are set while the Transmit Shift Register is loaded with data.
PIC18F87K22 FAMILY 22.3 Once the TXREGx register transfers the data to the TSR register (occurs in one TCY), the TXREGx is empty and the TXxIF flag bit is set. The interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TXxIE. TXxIF is set regardless of the state of enable bit, TXxIE; it cannot be cleared in software. It will reset only when new data is loaded into the TXREGx register.
PIC18F87K22 FAMILY FIGURE 22-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX1/DT1 Pin bit 0 bit 2 bit 1 bit 6 bit 7 RC6/TX1/CK1 Pin Write to TXREG1 reg TX1IF bit TRMT bit TXEN bit Note: This example is equally applicable to EUSART2 (RG1/TX2/CK2/AN19/C3OUT and RG2/RX2/DT2/AN18/C3INA).
PIC18F87K22 FAMILY 22.3.2 EUSART SYNCHRONOUS MASTER RECEPTION 3. 4. 5. 6. Ensure bits, CREN and SREN, are clear. If interrupts are desired, set enable bit, RCxIE. If 9-bit reception is desired, set bit, RX9. If a single reception is required, set bit, SREN. For continuous reception, set bit, CREN. 7. Interrupt flag bit, RCxIF, will be set when reception is complete and an interrupt will be generated if the enable bit, RCxIE, was set. 8.
PIC18F87K22 FAMILY TABLE 22-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF TMR1GIF TMR2IF TMR1IF PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE TMR1GIE TMR2IE TMR1IE IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP TMR1GIP TMR2IP TMR1IP PIR3 TMR5GIF — RC2IF TX2IF CTMUIF CCP2IF CCP1IF RTCCIF PIE3 TMR5GIE — RC2IE TX2IE CTM
PIC18F87K22 FAMILY 22.4 e) EUSART Synchronous Slave Mode Synchronous Slave mode is entered by clearing bit, CSRC (TXSTAx<7>). This mode differs from the Synchronous Master mode in that the shift clock is supplied externally at the CKx pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in any low-power mode. 22.4.1 To set up a Synchronous Slave Transmission: 1. 2. 3. 4. 5.
PIC18F87K22 FAMILY 22.4.2 EUSART SYNCHRONOUS SLAVE RECEPTION To set up a Synchronous Slave Reception: 1. The operation of the Synchronous Master and Slave modes is identical except in the case of Sleep, or any Idle mode, and bit, SREN, which is a “don’t care” in Slave mode. 2. 3. 4. 5. If receive is enabled by setting the CREN bit prior to entering Sleep or any Idle mode, then a word may be received while in this low-power mode.
PIC18F87K22 FAMILY 23.0 12-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The Analog-to-Digital (A/D) Converter module in the PIC18F87K22 family of devices has 16 inputs for the 64-pin devices and 24 inputs for the 80-pin devices. This module allows conversion of an analog input signal to a corresponding 12-bit digital number.
PIC18F87K22 FAMILY 23.2 A/D Registers 23.2.
PIC18F87K22 FAMILY REGISTER 23-2: ADCON1: A/D CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRIGSEL1 TRIGSEL0 VCFG1 VCFG0 VNCFG CHSN2 CHSN1 CHSN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 TRIGSEL<1:0>: Special Trigger Select bits 11 = Selects the special trigger from the RTCC 10 = Selects the special trigger from the Timer1 01 = Selects the special tr
PIC18F87K22 FAMILY REGISTER 23-3: ADCON2: A/D CONTROL REGISTER 2 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as ‘0’ bit 5-3 ACQT<2:0>: A/D Acquisition Time Select bits 111 = 20 TAD 110
PIC18F87K22 FAMILY 23.2.2 A/D RESULT REGISTERS The ADRESH:ADRESL register pair is where the 12-bit A/D result and extended sign bits (ADSGN) are loaded at the completion of a conversion. This register pair is 16 bits wide. The A/D module gives the flexibility of left or right justifying the 12-bit result in the 16-Bit Result register. The A/D Format Select bit (ADFM) controls this justification.
PIC18F87K22 FAMILY REGISTER 23-4: ADRESH: A/D RESULT HIGH BYTE REGISTER, LEFT JUSTIFIED (ADFM = 0) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x ADRES11 ADRES10 ADRES9 ADRES8 ADRES7 ADRES6 ADRES5 ADRES4 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown ADRES<11:4>: A/D Result High Byte bits REGISTER 23-5: ADRESL: A/D RESULT HIGH BYTE REGISTER, LEFT JUSTIF
PIC18F87K22 FAMILY REGISTER 23-6: ADRESH: A/D RESULT HIGH BYTE REGISTER, RIGHT JUSTIFIED (ADFM = 1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x ADSGN ADSGN ADSGN ADSGN ADRES11 ADRES10 ADRES9 ADRES8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 ADSGN: A/D Result Sign bit 1 = A/D result is negative 0 = A/D result is positive bit 3-0 ADRESH<11:8>: A/D Result High Byte bit
PIC18F87K22 FAMILY The ANCONx registers are used to configure the operation of the I/O pin associated with each analog channel. Clearing an ANSELx bit configures the corresponding pin (ANx) to operate as a digital only I/O. Setting a bit configures the pin to operate as an analog input for either the A/D Converter or the comparator module, with all digital peripherals disabled and digital inputs read as ‘0’.
PIC18F87K22 FAMILY REGISTER 23-10: ANCON2: A/D PORT CONFIGURATION REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 ANSEL23(1) ANSEL22(1) ANSEL21(1) ANSEL20(1) ANSEL19 ANSEL18 ANSEL17 ANSEL16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: x = Bit is unknown ANSEL<23:16>: Analog Port Configuration bits (AN23 through AN16)(1) 1 = Pin is configured as an analog
PIC18F87K22 FAMILY FIGURE 23-4: A/D BLOCK DIAGRAM CHS<4:0> 11111 VDDCORE 11101 Reserved Temperature Diode 11100 12-Bit A/D Converter 1.
PIC18F87K22 FAMILY After the A/D module has been configured as desired, the selected channel must be acquired before the conversion can start. The analog input channels must have their corresponding TRIS bits selected as inputs. To determine acquisition time, see Section 23.3 “A/D Acquisition Requirements”. After this acquisition time has elapsed, the A/D conversion can be started. An acquisition time can be programmed to occur between setting the GO/DONE bit and the actual start of the conversion. 2.
PIC18F87K22 FAMILY 23.3 A/D Acquisition Requirements For the A/D Converter to meet its specified accuracy, the Charge Holding (CHOLD) capacitor must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 23-5. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD).
PIC18F87K22 FAMILY 23.4 Selecting and Configuring Automatic Acquisition Time The ADCON2 register allows the user to select an acquisition time that occurs each time the GO/DONE bit is set. When the GO/DONE bit is set, sampling is stopped and a conversion begins. The user is responsible for ensuring the required acquisition time has passed between selecting the desired input channel and setting the GO/DONE bit.
PIC18F87K22 FAMILY 23.7 ADRESH:ADRESL registers will continue to contain the value of the last completed conversion (or the last value written to the ADRESH:ADRESL registers). A/D Conversions Figure 23-6 shows the operation of the A/D Converter after the GO/DONE bit has been set and the ACQT<2:0> bits are cleared. A conversion is started after the following instruction to allow entry into Sleep mode before the conversion begins.
PIC18F87K22 FAMILY 23.
PIC18F87K22 FAMILY TABLE 23-2: REGISTERS ASSOCIATED WITH A/D MODULE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF TMR1GIF TMR2IF TMR1IF PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE TMR1GIE TMR2IE TMR1IE IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP TMR1GIP TMR2IP TMR1IP INTCON PIR3 TMR5GIF — RC2IF TX2IF CTMUIF CCP2IF CCP1IF RTCCIF PIE3 TMR5GIE — RC2IE TX2IE CTMUIE CCP2I
PIC18F87K22 FAMILY 24.0 COMPARATOR MODULE 24.1 The analog comparator module contains three comparators that can be independently configured in a variety of ways. The inputs can be selected from the analog inputs and two Internal Reference Voltages. The digital outputs are available at the pin level and can also be read through the control register. Multiple output and interrupt event generation are also available. A generic single comparator from the module is shown in Figure 24-1.
PIC18F87K22 FAMILY REGISTER 24-1: CMxCON: COMPARATOR CONTROL x REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CON: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled bit 6 COE: Comparator Output Enable bit 1 = Comparator output is pres
PIC18F87K22 FAMILY REGISTER 24-2: CMSTAT: COMPARATOR STATUS REGISTER R-x R-x R-x U-0 U-0 U-0 U-0 U-0 CMP3OUT CMP2OUT CMP1OUT — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 CMP<3:1>OUT: Comparator x Status bits If CPOL (CMxCON<5>)= 0 (non-inverted polarity): 1 = Comparator x’s VIN+ > VIN0 = Comparator x’s VIN+ < VINIf CPOL = 1 (inverted polarity): 1 = Comparator x’s
PIC18F87K22 FAMILY 24.2 Comparator Operation 24.3 Comparator Response Time A single comparator is shown in Figure 24-2, along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input, VIN-, the output of the comparator is a digital low level. When the analog input at VIN+ is greater than the analog input, VIN-, the output of the comparator is a digital high level.
PIC18F87K22 FAMILY 24.5 Comparator Control and Configuration Each comparator has up to eight possible combinations of inputs: up to four external analog inputs and one of two Internal Reference Voltages. All of the comparators allow a selection of the signal from pin, CxINA, or the voltage from the comparator reference (CVREF) on the non-inverting channel. This is compared to either CxINB, CxINC, C2INB/C2IND or the microcontroller’s fixed Internal Reference Voltage (VBG, 1.
PIC18F87K22 FAMILY FIGURE 24-4: COMPARATOR CONFIGURATIONS Comparator Off CON = 0, CREF = x, CCH<1:0> = xx COE VINCx VIN+ Off (Read as ‘0’) CxOUT Pin Comparator CxINC > CxINA Compare(2,3) CON = 1, CREF = 0, CCH<1:0> = 01 Comparator CxINB > CxINA Compare CON = 1, CREF = 0, CCH<1:0> = 00 COE COE CxINB CxINA VINVIN+ CxINC Cx CxOUT Pin Comparator CxIND > CxINA Compare(3) CON = 1, CREF = 0, CCH<1:0> = 10 CxINA VINVIN+ Cx CxOUT Pin Comparator VIRV > CxINA Compare CON = 1, CREF = 0, CCH<1:0> = 11
PIC18F87K22 FAMILY 24.6 Comparator Interrupts The comparator interrupt flag is set whenever any of the following occurs: • Low-to-high transition of the comparator output • High-to-low transition of the comparator output • Any change in the comparator output The comparator interrupt selection is done by the EVPOL<1:0> bits in the CMxCON register (CMxCON<4:3>). In order to provide maximum flexibility, the output of the comparator may be inverted using the CPOL bit in the CMxCON register (CMxCON<5>).
PIC18F87K22 FAMILY 24.7 To minimize power consumption while in Sleep mode, turn off the comparators (CON = 0) before entering Sleep. If the device wakes up from Sleep, the contents of the CMxCON register are not affected. Comparator Operation During Sleep When a comparator is active and the device is placed in Sleep mode, the comparator remains active and the interrupt is functional, if enabled. This interrupt will wake up the device from Sleep mode, when enabled.
PIC18F87K22 FAMILY 25.0 COMPARATOR VOLTAGE REFERENCE MODULE EQUATION 25-1: If CVRSS = 1: The comparator voltage reference is a 32-tap resistor ladder network that provides a selectable reference voltage. Although its primary purpose is to provide a reference for the analog comparators, it may also be used independently of them. A block diagram of the module is shown in Figure 25-1.
PIC18F87K22 FAMILY FIGURE 25-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM VREF+ AVDD CVRSS = 1 CVRSS = 0 CVR<4:0> R CVREN R R 32-to-1 MUX R 32 Steps R CVREF R R VREF- CVRSS = 1 CVRSS = 0 25.2 Voltage Reference Accuracy/Error The full range of voltage reference cannot be realized due to the construction of the module. The transistors on the top and bottom of the resistor ladder network (Figure 25-1) keep CVREF from approaching the reference source rails.
PIC18F87K22 FAMILY FIGURE 25-2: COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC18F87K22 CVREF Module R(1) Voltage Reference Output Impedance Note 1: TABLE 25-1: Name + – RF5 CVREF Output R is dependent upon the Voltage Reference Configuration bits, CVRCON<3:0> and CVRCON<5>.
PIC18F87K22 FAMILY NOTES: DS39960D-page 378 2009-2011 Microchip Technology Inc.
PIC18F87K22 FAMILY 26.0 HIGH/LOW-VOLTAGE DETECT (HLVD) The PIC18F87K22 family of devices has a High/LowVoltage Detect module (HLVD). This is a programmable circuit that sets both a device voltage trip point and the direction of change from that point. If the device experiences an excursion past the trip point in that direction, an interrupt flag is set. If the interrupt is enabled, the program execution branches to the interrupt vector address and the software responds to the interrupt.
PIC18F87K22 FAMILY The module is enabled by setting the HLVDEN bit (HLVDCON<4>). Each time the HLVD module is enabled, the circuitry requires some time to stabilize. The IRVST bit (HLVDCON<5>) is a read-only bit used to indicate when the circuit is stable. The module can only generate an interrupt after the circuit is stable and IRVST is set. trip point voltage.
PIC18F87K22 FAMILY 26.2 HLVD Setup To set up the HLVD module: 1. 2. 3. 4. 5. Select the desired HLVD trip point by writing the value to the HLVDL<3:0> bits. Set the VDIRMAG bit to detect high voltage (VDIRMAG = 1) or low voltage (VDIRMAG = 0). Enable the HLVD module by setting the HLVDEN bit. Clear the HLVD interrupt flag (PIR2<2>), which may have been set from a previous interrupt.
PIC18F87K22 FAMILY FIGURE 26-2: LOW-VOLTAGE DETECT OPERATION (VDIRMAG = 0) HLVDIF may not be Set CASE 1: VDD VHLVD HLVDIF Enable HLVD TIRVST IRVST Internal Reference is Stable CASE 2: HLVDIF Cleared in Software VDD VHLVD HLVDIF Enable HLVD TIRVST IRVST Internal Reference is Stable HLVDIF Cleared in Software HLVDIF Cleared in Software, HLVDIF Remains Set since HLVD Condition still Exists DS39960D-page 382 2009-2011 Microchip Technology Inc.
PIC18F87K22 FAMILY FIGURE 26-3: HIGH-VOLTAGE DETECT OPERATION (VDIRMAG = 1) CASE 1: HLVDIF may not be Set VHLVD VDD HLVDIF Enable HLVD TIRVST IRVST HLVDIF Cleared in Software Internal Reference is Stable CASE 2: VHLVD VDD HLVDIF Enable HLVD TIRVST IRVST Internal Reference is Stable HLVDIF Cleared in Software HLVDIF Cleared in Software, HLVDIF Remains Set since HLVD Condition still Exists Applications In many applications, it is desirable to detect a drop below, or rise above, a particular voltage
PIC18F87K22 FAMILY 26.6 Operation During Sleep 26.7 When enabled, the HLVD circuitry continues to operate during Sleep. If the device voltage crosses the trip point, the HLVDIF bit will be set and the device will wake up from Sleep. Device execution will continue from the interrupt vector address if interrupts have been globally enabled. TABLE 26-1: Effects of a Reset A device Reset forces all registers to their Reset state. This forces the HLVD module to be turned off.
PIC18F87K22 FAMILY 27.0 • • • • Control of response to edges Time measurement resolution of 1 nanosecond High-precision time measurement Time delay of external or internal signal asynchronous to system clock • Accurate current source suitable for capacitive measurement CHARGE TIME MEASUREMENT UNIT (CTMU) The Charge Time Measurement Unit (CTMU) is a flexible analog module that provides accurate differential time measurement between pulse sources, as well as asynchronous pulse generation.
PIC18F87K22 FAMILY 27.1 The CTMUCONH and CTMUCONL registers (Register 27-1 and Register 27-2) contain control bits for configuring the CTMU module edge source selection, edge source polarity selection, edge sequencing, A/D trigger, analog circuit capacitor discharge and enables. The CTMUICON register (Register 27-3) has bits for selecting the current source range and current source trim.
PIC18F87K22 FAMILY REGISTER 27-2: CTMUCONL: CTMU CONTROL LOW REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 EDG2POL: Edge 2 Polarity Select bit 1 = Edge 2 is programmed for a positive edge response 0 = Edge 2 is programmed for a negative edge response
PIC18F87K22 FAMILY REGISTER 27-3: CTMUICON: CTMU CURRENT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 ITRIM<5:0>: Current Source Trim bits 011111 = Maximum positive change from nominal current 011110 . . .
PIC18F87K22 FAMILY 27.2 CTMU Operation The CTMU works by using a fixed current source to charge a circuit. The type of circuit depends on the type of measurement being made. In the case of charge measurement, the current is fixed and the amount of time the current is applied to the circuit is fixed. The amount of voltage read by the A/D becomes a measurement of the circuit’s capacitance. In the case of time measurement, the current, as well as the capacitance of the circuit, is fixed.
PIC18F87K22 FAMILY 27.2.5 INTERRUPTS The CTMU sets its interrupt flag (PIR3<3>) whenever the current source is enabled, then disabled. An interrupt is generated only if the corresponding interrupt enable bit (PIE3<3>) is also set. If edge sequencing is not enabled (i.e., Edge 1 must occur before Edge 2), it is necessary to monitor the edge status bits and determine which edge occurred last and caused the interrupt. 27.
PIC18F87K22 FAMILY The CTMU current source may be trimmed with the trim bits in CTMUICON using an iterative process to get the exact current desired. Alternatively, the nominal value without adjustment may be used. That value may be stored by software for use in all subsequent capacitive or time measurements. To calculate the value for RCAL, the nominal current must be chosen. Then, the resistance can be calculated. For example, if the A/D Converter reference voltage is 3.3V, use 70% of full scale (or 2.
PIC18F87K22 FAMILY EXAMPLE 27-1: SETUP FOR CTMU CALIBRATION ROUTINES #include "p18cxxx.
PIC18F87K22 FAMILY EXAMPLE 27-2: CURRENT CALIBRATION ROUTINE #include "p18cxxx.h" #define COUNT 500 #define DELAY for(i=0;i
PIC18F87K22 FAMILY 27.4.2 CAPACITANCE CALIBRATION There is a small amount of capacitance from the internal A/D Converter sample capacitor, as well as stray capacitance from the circuit board traces and pads that affect the precision of capacitance measurements. A measurement of the stray capacitance can be taken by making sure the desired capacitance to be measured has been removed. After removing the capacitance to be measured: 1. 2. 3. 4. 5. 6. Initialize the A/D Converter and the CTMU.
PIC18F87K22 FAMILY EXAMPLE 27-3: CAPACITANCE CALIBRATION ROUTINE #include "p18cxxx.h" #define #define #define #define #define #define COUNT 25 ETIME COUNT*2.5 DELAY for(i=0;i
PIC18F87K22 FAMILY 27.5 Measuring Capacitance with the CTMU There are two ways to measure capacitance with the CTMU. The absolute method measures the actual capacitance value. The relative method only measures for any change in the capacitance. 27.5.1 ABSOLUTE CAPACITANCE MEASUREMENT For absolute capacitance measurements, both the current and capacitance calibration steps found in Section 27.4 “Calibrating the CTMU Module” should be followed. To perform these measurements: 1. 2. 3. 4. 5. 6. 7. 8.
PIC18F87K22 FAMILY EXAMPLE 27-4: ROUTINE FOR CAPACITIVE TOUCH SWITCH #include "p18cxxx.h" #define #define #define #define COUNT 500 DELAY for(i=0;i
PIC18F87K22 FAMILY 27.6 Measuring Time with the CTMU Module Time can be precisely measured after the ratio (C/I) is measured from the current and capacitance calibration step. To do that: 1. 2. 3. 4. 5. Initialize the A/D Converter and the CTMU. Set EDG1STAT. Set EDG2STAT. Perform an A/D conversion. Calculate the time between edges as T = (C/I) * V, where: • I is calculated in the current calibration step (Section 27.4.
PIC18F87K22 FAMILY 27.7 An example use of the external capacitor feature is interfacing with variable capacitive-based sensors, such as a humidity sensor. As the humidity varies, the pulse-width output on CTPLS will vary. An example use of the CTDIN feature is interfacing with a digital sensor. The CTPLS output pin can be connected to an input capture pin and the varying pulse width measured to determine the sensor’s output in the application.
PIC18F87K22 FAMILY 27.8 Measuring Temperature with the CTMU Module The CTMU, along with an internal diode, can be used to measure the temperature. The ADC can be connected to the internal diode and the CTMU module can EXAMPLE 27-5: source the current to the diode. The ADC reading will reflect the temperature. With the increase, the ADC readings will go low. This can be used for low-cost temperature measurement applications.
PIC18F87K22 FAMILY 27.9 Operation During Sleep/Idle Modes 27.9.1 27.10 Effects of a Reset on CTMU Upon Reset, all registers of the CTMU are cleared. This disables the CTMU module, turns off its current source and returns all configuration options to their default settings. The module needs to be re-initialized following any Reset. SLEEP MODE When the device enters any Sleep mode, the CTMU module current source is always disabled.
PIC18F87K22 FAMILY NOTES: DS39960D-page 402 2009-2011 Microchip Technology Inc.
PIC18F87K22 FAMILY 28.0 SPECIAL FEATURES OF THE CPU The PIC18F87K22 family of devices includes several features intended to maximize reliability and minimize cost through elimination of external components.
PIC18F87K22 FAMILY TABLE 28-1: CONFIGURATION BITS AND DEVICE IDs File Name Bit 7 Bit 6 Bit 5 300000h CONFIG1L — XINST — 300001h CONFIG1H IESO FCMEN — 300002h CONFIG2L — 300003h CONFIG2H — WDTPS4 RETEN -1-1 1--1 FOSC2 FOSC1 FOSC0 00-0 1000 BOREN0 PWRTEN -111 1111 WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN1 WDTEN0 -111 1111 (2) (2) — RTCOSC ---- ---1 ECCPMX(2) CCP2MX 1--- 1-11 DEBUG — 300008h CONFIG5L CP7(1) 300009h CONFIG5H CPD 30000Ch CONFIG7L EBTR7 — BOREN1 300006h
PIC18F87K22 FAMILY REGISTER 28-1: CONFIG1L: CONFIGURATION REGISTER 1 LOW (BYTE ADDRESS 300000h) U-0 R/P-1 U-0 — XINST — R/P-1 R/P-1 SOSCSEL1 SOSCSEL0 R/P-1 U-0 R/P-1 INTOSCSEL — RETEN bit 7 bit 0 Legend: P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 XINST: Extended Instruction Set Enable bit 1 = Instruction set extension
PIC18F87K22 FAMILY REGISTER 28-2: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h) R/P-0 R/P-0 U-0 U-0 R/P-1 R/P-0 R/P-0 R/P-0 IESO FCMEN — PLLCFG(1) FOSC3(2) FOSC2(2) FOSC1(2) FOSC0(2) bit 7 bit 0 Legend: P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IESO: Internal/External Oscillator Switchover bit 1 = Two-Speed Start-up is enabled 0 = Two
PIC18F87K22 FAMILY REGISTER 28-3: U-0 — CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h) R/P-1 BORPWR1 R/P-1 (1) R/P-1 (1) BORPWR0 BORV1 R/P-1 (1) BORV0 (1) R/P-1 R/P-1 (2) BOREN1 R/P-1 (2) BOREN0 PWRTEN(2) bit 7 bit 0 Legend: P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-5 BORPWR<1:0>: BORMV Power-Level bits
PIC18F87K22 FAMILY REGISTER 28-4: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h) U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — WDTPS4 WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN1 WDTEN0 bit 7 bit 0 Legend: P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-2 WDTPS<4:0>: Watchdog Timer Postscale Select bits 10101-11111
PIC18F87K22 FAMILY REGISTER 28-5: U-1 CONFIG3L: CONFIGURATION REGISTER 3 LOW (BYTE ADDRESS 300004h) U-1 (1) BW WAIT (1) U-1 ABW1 U-1 (1) ABW0 U-1 (1) EASHFT (1) U-0 U-0 R/P-1 — — RTCOSC bit 7 bit 0 Legend: P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WAIT: External Bus Wait Enable bit(1) 1 = Wait states on the external bus are disabled 0 = Wait states on
PIC18F87K22 FAMILY REGISTER 28-6: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h) R/P-1 U-0 U-0 U-0 R/P-1 U-0 R/P-1 R/P-1 MCLRE — — — MSSPMSK — ECCPMX(1) CCP2MX bit 7 bit 0 Legend: P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 MCLRE: MCLR Pin Enable bit 1 = MCLR pin is enabled; RG5 input pin is disabled 0 = RG5 input pin is enabled; MCLR is disabled bit 6-4
PIC18F87K22 FAMILY REGISTER 28-7: CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h) R/P-1 U-0 U-0 R/P-0 U-0 U-0 U-0 R/P-1 DEBUG — — BBSIZ0 — — — STVREN bit 7 bit 0 Legend: P = Programmable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 DEBUG: Background Debugger Enable bit 1 = Background debugger is disabled, RB6 and RB7 are configured as general purpose I/O pi
PIC18F87K22 FAMILY REGISTER 28-8: CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h) R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 CP7(1) CP6(1) CP5(1) CP4(1) CP3 CP2 CP1 CP0 bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CP7: Code Protection bit(1) 1 = Block 7 is not code-protected(2) 0 = Block 7 is code-protected(2) bit 6 CP6: Code Protection
PIC18F87K22 FAMILY REGISTER 28-9: CONFIG5H: CONFIGURATION REGISTER 5 HIGH (BYTE ADDRESS 300009h) R/C-1 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0 CPD CPB — — — — — — bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CPD: Data EEPROM Code Protection bit 1 = Data EEPROM is not code-protected 0 = Data EEPROM is code-protected bit 6 CPB: Boot Block Code Protection bit 1 = Boot
PIC18F87K22 FAMILY REGISTER 28-10: CONFIG6L: CONFIGURATION REGISTER 6 LOW (BYTE ADDRESS 30000Ah) R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 WRT7(1) WRT6(1) WRT5(1) WRT4(1) WRT3 WRT2 WRT1 WRT0 bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 WRT7: Write Protection bit(1) 1 = Block 7 is not write-protected(2) 0 = Block 7 is write-protected(2) bit 6 WRT6: Wri
PIC18F87K22 FAMILY REGISTER 28-11: CONFIG6H: CONFIGURATION REGISTER 6 HIGH (BYTE ADDRESS 30000Bh) R/C-1 R/C-1 R-1 U-0 U-0 U-0 U-0 U-0 WRTD WRTB WRTC(1) — — — — — bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 WRTD: Data EEPROM Write Protection bit 1 = Data EEPROM is not write-protected 0 = Data EEPROM is write-protected bit 6 WRTB: Boot Block Write Protection
PIC18F87K22 FAMILY REGISTER 28-12: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch) R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 EBTR7(1,3) EBTR6(1,3) EBTR5(1,3) EBTR4(1,3) EBTR3(3) EBTR2(3) EBTR1(3) EBTR0(3) bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EBTR7: Table Read Protection bit(1,3) 1 = Block 7 is not protected from
PIC18F87K22 FAMILY REGISTER 28-13: CONFIG7H: CONFIGURATION REGISTER 7 HIGH (BYTE ADDRESS 30000Dh) U-0 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0 — EBTRB(2) — — — — — — bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 EBTRB: Boot Block Table Read Protection bit(2) 1 = Boot block is not protected from table reads executed i
PIC18F87K22 FAMILY REGISTER 28-14: DEVID1: DEVICE ID REGISTER 1 FOR THE PIC18F87K22 FAMILY R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 DEV<2:0>: Device ID bits Devices with DEV<10:3> of ‘0101 0010’ (see DEVID2): 010 = PIC18F65K22 000 = PIC18F66K22 101 = PIC18F85K22 011 = PIC18F86K22 Devices with DEV<10:3> of ‘0101 0001’
PIC18F87K22 FAMILY 28.2 The WDT can be operated in one of four modes as determined by the WDTEN<1:0> (CONFIG2H<1:0> bits. The four modes are: Watchdog Timer (WDT) For the PIC18F87K22 family of devices, the WDT is driven by the LF-INTOSC source. When the WDT is enabled, the clock source is also enabled. The nominal WDT period is 4 ms and has the same stability as the LF-INTOSC oscillator.
PIC18F87K22 FAMILY 28.2.1 CONTROL REGISTER Register 28-16 shows the WDTCON register. This is a readable and writable register which contains a control bit that allows software to override the WDT Enable Configuration bit, but only if the Configuration bit has disabled the WDT.
PIC18F87K22 FAMILY 28.3 On-Chip Voltage Regulator All of the PIC18F87K22 family devices power their core digital logic at a nominal 3.3V. For designs that are required to operate at a higher typical voltage, such as 5V, all family devices incorporate two on-chip regulators that allow the device to run its core logic from VDD.
PIC18F87K22 FAMILY 28.3.2 OPERATION OF REGULATOR IN SLEEP The difference in the two regulators’ operation arises with Sleep mode. The ultra low-power regulator gives the device the lowest current in the Regulator Enabled mode. The on-chip regulator can go into a lower power mode, when the device goes to Sleep, by setting the REGSLP bit (WDTCON<7>). This puts the regulator in a Standby mode so that the device consumes much less current.
PIC18F87K22 FAMILY 28.4 In all other power-managed modes, Two-Speed Startup is not used. The device will be clocked by the currently selected clock source until the primary clock source becomes available. The setting of the IESO bit is ignored.
PIC18F87K22 FAMILY 28.5 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) allows the microcontroller to continue operation in the event of an external oscillator failure by automatically switching the device clock to the internal oscillator block. The FSCM function is enabled by setting the FCMEN Configuration bit. When FSCM is enabled, the LF-INTOSC oscillator runs at all times to monitor clocks to peripherals and provide a backup clock in the event of a clock failure.
PIC18F87K22 FAMILY FIGURE 28-5: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure Device Clock Output CM Output (Q) Failure Detected OSCFIF CM Test Note: 28.5.3 FSCM INTERRUPTS IN POWER-MANAGED MODES By entering a power-managed mode, the clock multiplexer selects the clock source selected by the OSCCON register. Fail-Safe Clock Monitoring of the power-managed clock source resumes in the power-managed mode.
PIC18F87K22 FAMILY 28.6 Each of the blocks has three code protection bits associated with them. They are: Program Verification and Code Protection • Code-Protect bit (CPx) • Write-Protect bit (WRTx) • External Block Table Read bit (EBTRx) The user program memory is divided into four blocks for the PIC18FX5K22 and PIC18FX6K22 devices, and eight blocks for PIC18FX7K22 devices. One of these is a boot block of 1 or 2 Kbytes. The remainder of the memory is divided into blocks on binary boundaries.
PIC18F87K22 FAMILY TABLE 28-4: SUMMARY OF CODE PROTECTION REGISTERS File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 300008h CONFIG5L CP7(1) CP6(1) CP5(1) CP4(1) CP3 CP2 CP1 CP0 300009h CONFIG5H CPD CPB — — — — — — WRT3 WRT2 WRT1 WRT0 — — — — EBTR3 EBTR2 EBTR1 EBTR0 — — — — 30000Ah CONFIG6L WRT7 (1) 30000Bh CONFIG6H WRTD 30000Ch CONFIG7L EBTR7(1) 30000Dh CONFIG7H — (1) WRT6 WRTB EBTR6 (1) EBTRB WRT5 (1) WRT4 WRTC EBTR5 (1) (1) — (1)
PIC18F87K22 FAMILY FIGURE 28-8: EXTERNAL BLOCK TABLE READ (EBTRx) DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h 0007FFh 000800h TBLPTR = 0008FFh WRTB, EBTRB = 11 WRT0, EBTR0 = 10 003FFFh 004000h PC = 007FFEh WRT1, EBTR1 = 11 TBLRD* 007FFFh 008000h WRT2, EBTR2 = 11 00BFFFh 00C000h WRT3, EBTR3 = 11 00FFFFh Results: All table reads from external blocks to Blockn are disabled whenever EBTRx = 0. The TABLAT register returns a value of ‘0’.
PIC18F87K22 FAMILY 28.6.2 DATA EEPROM CODE PROTECTION The entire data EEPROM is protected from external reads and writes by two bits: CPD and WRTD. CPD inhibits external reads and writes of data EEPROM. WRTD inhibits internal and external writes to data EEPROM. The CPU can always read data EEPROM under normal operation, regardless of the protection bit settings. 28.6.3 CONFIGURATION REGISTER PROTECTION The Configuration registers can be write-protected.
PIC18F87K22 FAMILY NOTES: DS39960D-page 430 2009-2011 Microchip Technology Inc.
PIC18F87K22 FAMILY 29.0 INSTRUCTION SET SUMMARY The PIC18F87K22 family of devices incorporates the standard set of 75 PIC18 core instructions, as well as an extended set of 8 new instructions for the optimization of code that is recursive or that utilizes a software stack. The extended set is discussed later in this section. 29.
PIC18F87K22 FAMILY TABLE 29-1: OPCODE FIELD DESCRIPTIONS Field a bbb BSR C, DC, Z, OV, N d dest f fs fd GIE k label mm * *+ *+* n PC PCL PCH PCLATH PCLATU PD PRODH PRODL s TBLPTR TABLAT TO TOS u WDT WREG x zs zd { } [text] (text) [expr] < > italics DS39960D-page 432 Description RAM access bit: a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register Bit address within an 8-bit file register (0 to 7). Bank Select Register.
PIC18F87K22 FAMILY FIGURE 29-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 15 10 9 OPCODE Example Instruction 8 7 d 0 a f (FILE #) ADDWF MYREG, W, B d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 0 OPCODE 15 f (Source FILE #) 12 11 MOVFF MYREG1, MYREG2 0 f (Destination FIL
PIC18F87K22 FAMILY TABLE 29-2: PIC18F87K22 FAMILY INSTRUCTION SET Mnemonic, Operands 16-Bit Instruction Word Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED OPERATIONS ADDWF ADDWFC ANDWF CLRF COMF CPFSEQ CPFSGT CPFSLT DECF DECFSZ DCFSNZ INCF INCFSZ INFSNZ IORWF MOVF MOVFF f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a fs, fd MOVWF MULWF NEGF RLCF RLNCF RRCF RRNCF SETF SUBFWB f, a f, a f, a f, d, a f, d, a f, d, a
PIC18F87K22 FAMILY TABLE 29-2: PIC18F87K22 FAMILY INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes BIT-ORIENTED OPERATIONS BCF BSF BTFSC BTFSS BTG f, b, a f, b, a f, b, a f, b, a f, b, a Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Bit Toggle f 1 1 1 (2 or 3) 1 (2 or 3) 1 1001 1000 1011 1010 0111 bbba bbba bbba bbba bbba ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff None None None None None
PIC18F87K22 FAMILY TABLE 29-2: PIC18F87K22 FAMILY INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes LITERAL OPERATIONS ADDLW ANDLW IORLW LFSR k k k f, k MOVLB MOVLW MULLW RETLW SUBLW XORLW k k k k k k Add Literal and WREG AND Literal with WREG Inclusive OR Literal with WREG Move literal (12-bit) 2nd word 1st word to FSR(f) Move Literal to BSR<3:0> Move Literal to WREG Multiply Literal with WREG Return with Literal in WREG Sub
PIC18F87K22 FAMILY 29.1.1 STANDARD INSTRUCTION SET ADDLW ADD Literal to W ADDWF ADD W to f Syntax: ADDLW Syntax: ADDWF Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) + (f) dest Status Affected: N, OV, C, DC, Z k Operands: 0 k 255 Operation: (W) + k W Status Affected: N, OV, C, DC, Z Encoding: 0000 1111 kkkk kkkk Description: The contents of W are added to the 8-bit literal ‘k’ and the result is placed in W.
PIC18F87K22 FAMILY ADDWFC ADD W and Carry bit to f ANDLW AND Literal with W Syntax: ADDWFC Syntax: ANDLW Operands: 0 f 255 d [0,1] a [0,1] f {,d {,a}} Operation: (W) + (f) + (C) dest Status Affected: N,OV, C, DC, Z Encoding: 0010 Description: 00da ffff Add W, the Carry flag and data memory location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in data memory location ‘f’. If ‘a’ is ‘0’, the Access Bank is selected.
PIC18F87K22 FAMILY ANDWF AND W with f BC Branch if Carry Syntax: ANDWF Syntax: BC Operands: 0 f 255 d [0,1] a [0,1] f {,d {,a}} Operation: (W) .AND. (f) dest Status Affected: N, Z Encoding: Description: 0001 Operands: -128 n 127 Operation: if Carry bit is ‘1’, (PC) + 2 + 2n PC Status Affected: None Encoding: 01da ffff ffff Description: The contents of W are ANDed with register ‘f’. If ‘d’ is ‘0’, the result is stored in W.
PIC18F87K22 FAMILY BCF Bit Clear f BN Branch if Negative Syntax: BCF Syntax: BN Operands: 0 f 255 0b7 a [0,1] f, b {,a} Operation: 0 f Status Affected: None Encoding: 1001 Description: Operands: -128 n 127 Operation: if Negative bit is ‘1’, (PC) + 2 + 2n PC Status Affected: None Encoding: bbba ffff ffff Description: Bit ‘b’ in register ‘f’ is cleared.
PIC18F87K22 FAMILY BNC Branch if Not Carry BNN Branch if Not Negative Syntax: BNC Syntax: BNN n n Operands: -128 n 127 Operands: -128 n 127 Operation: if Carry bit is ‘0’, (PC) + 2 + 2n PC Operation: if Negative bit is ‘0’, (PC) + 2 + 2n PC Status Affected: None Status Affected: None Encoding: Description: 1110 0011 nnnn nnnn If the Carry bit is ‘0’, then the program will branch. Encoding: Description: The 2’s complement number ‘2n’ is added to the PC.
PIC18F87K22 FAMILY BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: BNOV Syntax: BNZ n n Operands: -128 n 127 Operands: -128 n 127 Operation: if Overflow bit is ‘0’, (PC) + 2 + 2n PC Operation: if Zero bit is ‘0’, (PC) + 2 + 2n PC Status Affected: None Status Affected: None Encoding: 1110 Description: 0101 nnnn nnnn If the Overflow bit is ‘0’, then the program will branch. Encoding: Description: The 2’s complement number ‘2n’ is added to the PC.
PIC18F87K22 FAMILY BRA Unconditional Branch BSF Bit Set f Syntax: BRA Syntax: BSF Operands: 0 f 255 0b7 a [0,1] Operation: 1 f Status Affected: None n Operands: -1024 n 1023 Operation: (PC) + 2 + 2n PC Status Affected: None Encoding: Description: 1101 1 Cycles: 2 No operation Example: nnnn nnnn Add the 2’s complement number ‘2n’ to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n.
PIC18F87K22 FAMILY BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set Syntax: BTFSC f, b {,a} Syntax: BTFSS f, b {,a} Operands: 0 f 255 0b7 a [0,1] Operands: 0 f 255 0b<7 a [0,1] Operation: skip if (f) = 0 Operation: skip if (f) = 1 Status Affected: None Status Affected: None Encoding: Description: 1011 bbba ffff ffff If bit ‘b’ in register ‘f’ is ‘0’, then the next instruction is skipped.
PIC18F87K22 FAMILY BTG Bit Toggle f BOV Branch if Overflow Syntax: BTG f, b {,a} Syntax: BOV Operands: 0 f 255 0b<7 a [0,1] Operation: (f) f Status Affected: None Encoding: Description: 0111 Operands: -128 n 127 Operation: if Overflow bit is ‘1’, (PC) + 2 + 2n PC Status Affected: None Encoding: bbba ffff ffff Description: Bit ‘b’ in data memory location, ‘f’, is inverted.
PIC18F87K22 FAMILY BZ Branch if Zero CALL Subroutine Call Syntax: BZ Syntax: CALL k {,s} n Operands: -128 n 127 Operands: Operation: if Zero bit is ‘1’, (PC) + 2 + 2n PC 0 k 1048575 s [0,1] Operation: Status Affected: None (PC) + 4 TOS, k PC<20:1>; if s = 1 (W) WS, (STATUS) STATUSS, (BSR) BSRS Status Affected: None Encoding: 1110 Description: 0000 nnnn nnnn If the Zero bit is ‘1’, then the program will branch.
PIC18F87K22 FAMILY CLRF Clear f Syntax: CLRF Operands: 0 f 255 a [0,1] f {,a} Operation: 000h f, 1Z Status Affected: Z Encoding: Description: 0110 101a ffff ffff Clears the contents of the specified register.
PIC18F87K22 FAMILY COMF Complement f CPFSEQ Syntax: COMF Syntax: CPFSEQ Operands: 0 f 255 a [0,1] Operation: (f) – (W), skip if (f) = (W) (unsigned comparison) Status Affected: None f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operation: f dest Status Affected: N, Z Encoding: 0001 Description: 11da ffff ffff The contents of register ‘f’ are complemented. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’.
PIC18F87K22 FAMILY CPFSGT Compare f with W, Skip if f > W CPFSLT Compare f with W, Skip if f < W Syntax: CPFSGT Syntax: CPFSLT Operands: 0 f 255 a [0,1] Operands: 0 f 255 a [0,1] Operation: (f) –W), skip if (f) > (W) (unsigned comparison) Operation: (f) –W), skip if (f) < (W) (unsigned comparison) Status Affected: None Status Affected: None Encoding: Description: 0110 f {,a} 010a ffff ffff Compares the contents of data memory location ‘f’ to the contents of the W by
PIC18F87K22 FAMILY DAW Decimal Adjust W Register DECF Decrement f Syntax: DAW Syntax: DECF f {,d {,a}} Operands: None Operands: Operation: If [W<3:0> > 9] or [DC = 1], then (W<3:0>) + 6 W<3:0>; else (W<3:0>) W<3:0> 0 f 255 d [0,1] a [0,1] Operation: (f) – 1 dest Status Affected: C, DC, N, OV, Z Encoding: If [W<7:4> > 9] or [C = 1], then (W<7:4>) + 6 W<7:4>; C =1; else (W<7:4>) W<7:4> Status Affected: Description: 0000 0000 0000 0111 Description: DAW adjusts the 8
PIC18F87K22 FAMILY DECFSZ Decrement f, Skip if 0 DCFSNZ Decrement f, Skip if Not 0 Syntax: DECFSZ f {,d {,a}} Syntax: DCFSNZ Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) – 1 dest, skip if result = 0 Operation: (f) – 1 dest, skip if result 0 Status Affected: None Status Affected: None Encoding: Description: 0010 11da ffff ffff The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in W.
PIC18F87K22 FAMILY GOTO Unconditional Branch INCF Increment f Syntax: GOTO k Syntax: INCF Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) + 1 dest Status Affected: C, DC, N, OV, Z Operands: 0 k 1048575 Operation: k PC<20:1> Status Affected: None Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 1111 k19kkk k7kkk kkkk kkkk0 kkkk8 Description: GOTO allows an unconditional branch anywhere within entire 2-Mbyte memory range.
PIC18F87K22 FAMILY INCFSZ Increment f, Skip if 0 INFSNZ Increment f, Skip if Not 0 Syntax: INCFSZ Syntax: INFSNZ 0 f 255 d [0,1] a [0,1] f {,d {,a}} f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operands: Operation: (f) + 1 dest, skip if result = 0 Operation: (f) + 1 dest, skip if result 0 Status Affected: None Status Affected: None Encoding: Description: 0011 11da ffff ffff The contents of register ‘f’ are incremented.
PIC18F87K22 FAMILY IORLW Inclusive OR Literal with W IORWF Inclusive OR W with f Syntax: IORLW k Syntax: IORWF Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) .OR. (f) dest Status Affected: N, Z Operands: 0 k 255 Operation: (W) .OR. k W Status Affected: N, Z Encoding: 0000 1001 kkkk kkkk Description: The contents of W are ORed with the eight-bit literal ‘k’. The result is placed in W.
PIC18F87K22 FAMILY LFSR Load FSR MOVF Move f Syntax: LFSR f, k Syntax: MOVF Operands: 0f2 0 k 4095 Operands: Operation: k FSRf 0 f 255 d [0,1] a [0,1] Status Affected: None Operation: f dest Status Affected: N, Z Encoding: 1110 1111 1110 0000 00ff k7kkk k11kkk kkkk Description: The 12-bit literal ‘k’ is loaded into the file select register pointed to by ‘f’.
PIC18F87K22 FAMILY MOVFF Move f to f MOVLB Move Literal to Low Nibble in BSR Syntax: MOVFF fs,fd Syntax: MOVLB k Operands: 0 fs 4095 0 fd 4095 Operands: 0 k 255 Operation: k BSR Operation: (fs) fd Status Affected: None Status Affected: None Encoding: 1st word (source) 2nd word (destin.) Encoding: 1100 1111 Description: ffff ffff ffff ffff ffffs ffffd The contents of source register, ‘fs’, are moved to destination register ‘fd’.
PIC18F87K22 FAMILY MOVLW Move Literal to W MOVWF Move W to f Syntax: MOVLW k Syntax: MOVWF Operands: 0 f 255 a [0,1] Operation: (W) f Status Affected: None Operands: 0 k 255 Operation: kW Status Affected: None Encoding: 0000 1110 kkkk kkkk The eight-bit literal ‘k’ is loaded into W.
PIC18F87K22 FAMILY MULLW Multiply Literal with W MULWF Multiply W with f Syntax: MULLW Syntax: MULWF Operands: 0 f 255 a [0,1] Operation: (W) x (f) PRODH:PRODL Status Affected: None k Operands: 0 k 255 Operation: (W) x k PRODH:PRODL Status Affected: None Encoding: Description: 0000 1101 kkkk kkkk An unsigned multiplication is carried out between the contents of W and the 8-bit literal ‘k’. The 16-bit result is placed in the PRODH:PRODL register pair.
PIC18F87K22 FAMILY NEGF Negate f Syntax: NEGF Operands: 0 f 255 a [0,1] f {,a} Operation: (f) + 1 f Status Affected: N, OV, C, DC, Z Encoding: Description: 0110 110a ffff If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 29.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details.
PIC18F87K22 FAMILY POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: POP Syntax: PUSH Operands: None Operands: None Operation: (TOS) bit bucket Operation: (PC + 2) TOS Status Affected: None Status Affected: None Encoding: 0000 0000 0000 0110 Encoding: 0000 0000 0000 0101 Description: The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack.
PIC18F87K22 FAMILY RCALL Relative Call RESET Reset Syntax: RCALL Syntax: RESET n Operands: -1024 n 1023 Operands: None Operation: (PC) + 2 TOS, (PC) + 2 + 2n PC Operation: Reset all registers and flags that are affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: Description: 1101 Words: 1 Cycles: 2 Q Cycle Activity: Q1 Decode No operation Example: 1nnn nnnn nnnn Subroutine call with a jump up to 1K from the current location.
PIC18F87K22 FAMILY RETFIE Return from Interrupt RETLW Return Literal to W Syntax: RETFIE {s} Syntax: RETLW k Operands: s [0,1] Operands: 0 k 255 Operation: (TOS) PC, 1 GIE/GIEH or PEIE/GIEL; if s = 1, (WS) W, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged Operation: k W, (TOS) PC, PCLATU, PCLATH are unchanged Status Affected: None Status Affected: 0000 Description: 0000 0001 1 Cycles: 2 1100 kkkk kkkk Description: W is loaded with the 8-bit liter
PIC18F87K22 FAMILY RETURN Return from Subroutine RLCF Rotate Left f through Carry Syntax: RETURN {s} Syntax: RLCF Operands: s [0,1] Operands: Operation: (TOS) PC; if s = 1, (WS) W, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged 0 f 255 d [0,1] a [0,1] Operation: (f) dest, (f<7>) C, (C) dest<0> Status Affected: C, N, Z Status Affected: None Encoding: Description: 0000 1 Cycles: 2 No operation Example: 0000 0001 001s Description: Ret
PIC18F87K22 FAMILY RLNCF Rotate Left f (No Carry) RRCF Rotate Right f through Carry Syntax: RLNCF Syntax: RRCF Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) dest, (f<7>) dest<0> Operation: Status Affected: N, Z (f) dest, (f<0>) C, (C) dest<7> Status Affected: C, N, Z Encoding: 0100 Description: f {,d {,a}} 01da ffff ffff The contents of register ‘f’ are rotated one bit to the left.
PIC18F87K22 FAMILY RRNCF Rotate Right f (No Carry) SETF Set f Syntax: RRNCF Syntax: SETF Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 a [0,1] Operation: FFh f Operation: (f) dest, (f<0>) dest<7> Status Affected: None Status Affected: N, Z Encoding: Description: 0100 f {,d {,a}} 00da Encoding: ffff ffff Description: The contents of register ‘f’ are rotated one bit to the right. If ‘d’ is ‘0’, the result is placed in W.
PIC18F87K22 FAMILY SLEEP Enter Sleep Mode SUBFWB Subtract f from W with Borrow Syntax: SLEEP Syntax: SUBFWB Operands: None Operands: Operation: 00h WDT, 0 WDT postscaler, 1 TO, 0 PD 0 f 255 d [0,1] a [0,1] Operation: (W) – (f) – (C) dest Status Affected: N, OV, C, DC, Z Status Affected: TO, PD Encoding: 0000 Description: Encoding: 0000 0000 0011 Description: The Power-Down status bit (PD) is cleared. The Time-out status bit (TO) is set.
PIC18F87K22 FAMILY SUBLW Subtract W from Literal SUBWF Subtract W from f Syntax: SUBLW k Syntax: SUBWF Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) – (W) dest Status Affected: N, OV, C, DC, Z Operands: 0 k 255 Operation: k – (W) W Status Affected: N, OV, C, DC, Z Encoding: 0000 1000 kkkk kkkk Description: W is subtracted from the eight-bit literal ‘k’. The result is placed in W.
PIC18F87K22 FAMILY SUBWFB Subtract W from f with Borrow SWAPF Swap f Syntax: SUBWFB Syntax: SWAPF f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) – (W) – (C) dest Operation: Status Affected: N, OV, C, DC, Z (f<3:0>) dest<7:4>, (f<7:4>) dest<3:0> Status Affected: None Encoding: 0101 Description: f {,d {,a}} 10da ffff ffff Subtract W and the Carry flag (borrow) from register ‘f’ (2’s complement method).
PIC18F87K22 FAMILY TBLRD Table Read TBLRD Table Read (Continued) Syntax: TBLRD ( *; *+; *-; +*) Example 1: TBLRD Operands: None Operation: if TBLRD *, (Prog Mem (TBLPTR)) TABLAT; TBLPTR – No Change if TBLRD *+, (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) + 1 TBLPTR if TBLRD *-, (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) – 1 TBLPTR if TBLRD +*, (TBLPTR) + 1 TBLPTR; (Prog Mem (TBLPTR)) TABLAT Status Affected: None Encoding: Description: 0000 0000 0000 Before Instruction TABLAT TBLPTR MEMORY(
PIC18F87K22 FAMILY TBLWT Table Write TBLWT Table Write (Continued) Syntax: TBLWT ( *; *+; *-; +*) Example 1: TBLWT *+; Operands: None Operation: if TBLWT*, (TABLAT) Holding Register; TBLPTR – No Change if TBLWT*+, (TABLAT) Holding Register; (TBLPTR) + 1 TBLPTR if TBLWT*-, (TABLAT) Holding Register; (TBLPTR) – 1 TBLPTR if TBLWT+*, (TBLPTR) + 1 TBLPTR; (TABLAT) Holding Register Status Affected: Example 2: None Encoding: Description: Before Instruction TABLAT = 55h TBLPTR = 00A35
PIC18F87K22 FAMILY TSTFSZ Test f, Skip if 0 XORLW Exclusive OR Literal with W Syntax: TSTFSZ f {,a} Syntax: XORLW k Operands: 0 f 255 a [0,1] Operands: 0 k 255 Operation: (W) .XOR. k W Operation: skip if f = 0 Status Affected: N, Z Status Affected: None Encoding: Description: Encoding: 0110 011a ffff ffff If ‘f’ = 0, the next instruction fetched during the current instruction execution is discarded and a NOP is executed, making this a two-cycle instruction.
PIC18F87K22 FAMILY XORWF Exclusive OR W with f Syntax: XORWF Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) .XOR. (f) dest Status Affected: N, Z Encoding: 0001 Description: f {,d {,a}} 10da ffff ffff Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank.
PIC18F87K22 FAMILY 29.2 A summary of the instructions in the extended instruction set is provided in Table 29-3. Detailed descriptions are provided in Section 29.2.2 “Extended Instruction Set”. The opcode field descriptions in Table 29-1 (page 432) apply to both the standard and extended PIC18 instruction sets.
PIC18F87K22 FAMILY 29.2.2 EXTENDED INSTRUCTION SET ADDFSR Add Literal to FSR ADDULNK Add Literal to FSR2 and Return Syntax: Operands: ADDFSR f, k 0 k 63 f [ 0, 1, 2 ] FSR(f) + k FSR(f) None 1110 1000 ffkk Syntax: Operands: Operation: ADDULNK k 0 k 63 FSR2 + k FSR2, (TOS) PC None 1110 1000 11kk Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode Example: kkkk The 6-bit literal ‘k’ is added to the contents of the FSR specified by ‘f’.
PIC18F87K22 FAMILY CALLW Subroutine Call Using WREG MOVSF Move Indexed to f Syntax: CALLW Syntax: MOVSF [zs], fd Operands: None Operands: Operation: (PC + 2) TOS, (W) PCL, (PCLATH) PCH, (PCLATU) PCU 0 zs 127 0 fd 4095 Operation: ((FSR2) + zs) fd Status Affected: None Status Affected: None Encoding: Description 0000 0000 0001 0100 First, the return address (PC + 2) is pushed onto the return stack.
PIC18F87K22 FAMILY MOVSS Move Indexed to Indexed PUSHL Store Literal at FSR2, Decrement FSR2 Syntax: MOVSS [zs], [zd] Syntax: PUSHL k Operands: 0 zs 127 0 zd 127 Operation: ((FSR2) + zs) ((FSR2) + zd) Status Affected: None Encoding: 1st word (source) 2nd word (dest.) 1110 1111 Description 1011 xxxx 1zzz xzzz zzzzs zzzzd The contents of the source register are moved to the destination register.
PIC18F87K22 FAMILY SUBFSR Subtract Literal from FSR SUBULNK Subtract Literal from FSR2 and Return Syntax: Operands: SUBFSR f, k 0 k 63 f [ 0, 1, 2 ] FSRf – k FSRf None 1110 1001 Syntax: Operands: Operation: SUBULNK k 0 k 63 FSR2 – k FSR2, (TOS) PC None 1110 1001 Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode ffkk kkkk The 6-bit literal ‘k’ is subtracted from the contents of the FSR specified by ‘f’.
PIC18F87K22 FAMILY 29.2.3 Note: BYTE-ORIENTED AND BIT-ORIENTED INSTRUCTIONS IN INDEXED LITERAL OFFSET MODE Enabling the PIC18 instruction set extension may cause legacy applications to behave erratically or fail entirely. In addition to eight new commands in the extended set, enabling the extended instruction set also enables Indexed Literal Offset Addressing (Section 6.6.1 “Indexed Addressing with Literal Offset”).
PIC18F87K22 FAMILY ADD W to Indexed (Indexed Literal Offset mode) BSF Syntax: ADDWF Syntax: BSF [k], b Operands: 0 k 95 d [0,1] Operands: 0 f 95 0b7 Operation: (W) + ((FSR2) + k) dest Operation: 1 ((FSR2) + k) Status Affected: N, OV, C, DC, Z Status Affected: None ADDWF Encoding: Description: [k] {,d} 0010 01d0 kkkk kkkk The contents of W are added to the contents of the register indicated by FSR2, offset by the value ‘k’. If ‘d’ is ‘0’, the result is stored in W.
PIC18F87K22 FAMILY 29.2.5 SPECIAL CONSIDERATIONS WITH MICROCHIP MPLAB® IDE TOOLS The latest versions of Microchip’s software tools have been designed to fully support the extended instruction set for the PIC18F87K22 family. This includes the MPLAB C18 C Compiler, MPASM assembly language and MPLAB Integrated Development Environment (IDE). When selecting a target device for software development, MPLAB IDE will automatically set default Configuration bits for that device.
PIC18F87K22 FAMILY 30.
PIC18F87K22 FAMILY 30.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 30.
PIC18F87K22 FAMILY 30.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC18F87K22 FAMILY 30.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 30.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
PIC18F87K22 FAMILY 31.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any digital only I/O pin with respect to VSS (except VDD).............................................
PIC18F87K22 FAMILY FIGURE 31-1: VOLTAGE-FREQUENCY GRAPH, REGULATOR ENABLED (INDUSTRIAL/EXTENDED)(1) 6V 5.5V Voltage (VDD) 5V PIC18F87K22 Family (Extended) 4V 3V 3V 1.8V 0 Note 1: 2: PIC18F87K22 Family (Industrial Only) 4 MHz 48 MHz Frequency 64 MHz(1) FMAX = 25 MHz in 8-Bit External Memory mode. For VDD values, 1.8V to 3V, FMAX = (VDD – 1.72)/0.02 MHz. FMAX = 64 MHz in all other modes. For VDD values, 1.8V to 3V, FMAX = (VDD – 1.72)/0.02 MHz.
PIC18F87K22 FAMILY 31.1 DC Characteristics: Supply Voltage PIC18F87K22 Family (Industrial/Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC18F87K22 Family (Industrial/Extended) Param Symbol No. D001 VDD Characteristic Supply Voltage Min Typ Max Units 1.8 1.8 — — 3.6 5.5 V V D001C AVDD Analog Supply Voltage VDD – 0.3 — VDD + 0.3 V D001D AVSS Analog Ground Potential VSS – 0.
PIC18F87K22 FAMILY 31.2 DC Characteristics: PIC18F87K22 Family (Industrial/Extended) Param No. Power-Down and Supply Current PIC18F87K22 Family (Industrial/Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Device Typ Max Units Conditions Power-Down Current (IPD)(1) All devices Note 1: 2: 3: 4: 5: 6: 10 500 nA -40°C 20 500 nA +25°C VDD = 1.
PIC18F87K22 FAMILY 31.2 DC Characteristics: PIC18F87K22 Family (Industrial/Extended) Param No. Device Power-Down and Supply Current PIC18F87K22 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Typ Max Units Conditions Supply Current (IDD)(2,3) All devices Note 1: 2: 3: 4: 5: 6: 5.3 10 µA -40°C 5.5 10 µA +25°C VDD = 1.8V(4) Regulator Disabled 5.
PIC18F87K22 FAMILY 31.2 DC Characteristics: PIC18F87K22 Family (Industrial/Extended) Param No. Note 1: 2: 3: 4: 5: 6: Device Power-Down and Supply Current PIC18F87K22 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Typ Max Units Conditions Supply Current (IDD) Cont.(2,3) All devices 2.1 5.5 µA -40°C 2.1 5.7 µA +25°C VDD = 1.8V(4) Regulator Disabled 2.2 6.
PIC18F87K22 FAMILY 31.2 DC Characteristics: PIC18F87K22 Family (Industrial/Extended) Param No. Device Power-Down and Supply Current PIC18F87K22 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Typ Max Units Conditions Supply Current (IDD) Cont.
PIC18F87K22 FAMILY 31.2 DC Characteristics: PIC18F87K22 Family (Industrial/Extended) Param No. Device Power-Down and Supply Current PIC18F87K22 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Typ Max Units Conditions Supply Current (IDD) Cont.(2,3) All devices 3.3 3.3 3.3 3.6 All devices 3.5 3.5 3.5 3.8 All devices 12 12 12 Note 1: 2: 3: 4: 5: 6: 5.
PIC18F87K22 FAMILY 31.2 DC Characteristics: PIC18F87K22 Family (Industrial/Extended) Param No. Device Power-Down and Supply Current PIC18F87K22 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Typ Max Units Conditions Supply Current (IDD) Cont.
PIC18F87K22 FAMILY 31.2 DC Characteristics: PIC18F87K22 Family (Industrial/Extended) Param No. Note 1: 2: 3: 4: 5: 6: Device Power-Down and Supply Current PIC18F87K22 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Typ Max Units Conditions Supply Current (IDD) Cont.(2,3) All devices 3.7 8.5 µA -40°C 5.4 10 µA +25°C VDD = 1.8V(4) Regulator Disabled 6.
PIC18F87K22 FAMILY 31.2 DC Characteristics: Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC18F87K22 Family (Industrial/Extended) Param No. D022 (IWDT) D022 (IWDT) D022A (IBOR) (IBOR) Device Note 1: 2: 3: 4: 5: 6: Typ Max Units Conditions Module Differential Currents (IWDT, IBOR, IHLVD, IOSCB, IAD) Watchdog Timer All devices 0.3 1 µA -40°C 0.3 1 µA +25°C 0.3 1 µA +85°C 0.
PIC18F87K22 FAMILY 31.2 DC Characteristics: PIC18F87K22 Family (Industrial/Extended) Param No. Device Power-Down and Supply Current PIC18F87K22 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Typ Max Units Conditions D025 Real-Time Clock/Calendar with SOSC Oscillator (IRTCC) All devices 0.7 2.7 µA Note 1: 2: 3: 4: 5: 6: -40°C 0.7 2.8 µA +25°C VDD = 1.8V(4) 1.
PIC18F87K22 FAMILY 31.3 DC Characteristics: PIC18F87K22 Family (Industrial/Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended DC CHARACTERISTICS Param Symbol No. Min Max VSS 0.15 VDD V VDD < 4.5V — 0.8 V 4.5V VDD 5.5V RC3, RC4 VSS 0.2 VDD V VDD < 4.5 RD5, RD6 VSS 1.5 V 4.5V VDD 5.5V D031A RC3, RC4 VSS 0.3 VDD V I2C™ enabled D031B RD5, RD6 VSS 0.
PIC18F87K22 FAMILY 31.3 DC Characteristics: PIC18F87K22 Family (Industrial/Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended DC CHARACTERISTICS Param Symbol No. VOL D080 Characteristic Min Max Units Conditions PORTA, PORTB, PORTC — 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40C to +125C PORTD, PORTE, PORTF, PORTG, PORTH, PORTJ — 0.6 V IOL = 3.5 mA, VDD = 4.5V, -40C to +125C — 0.
PIC18F87K22 FAMILY TABLE 31-1: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended DC CHARACTERISTICS Param No. Sym Characteristic Min Typ† Max Units Conditions Internal Program Memory Programming Specifications(1) D110 VPP Voltage on MCLR/VPP/RE5 pin D113 IDDP Supply Current during Programming D120 ED Byte Endurance D121 VDRW VDD for Read/Write VDD + 1.
PIC18F87K22 FAMILY TABLE 31-2: COMPARATOR SPECIFICATIONS Operating Conditions: 1.8V VDD 5V, -40°C TA +125°C (unless otherwise stated) Param No. Sym Characteristics Min Typ Max Units D300 VIOFF Input Offset Voltage — ±5.0 40 mV D301 VICM Input Common Mode Voltage — — AVDD – 1.
PIC18F87K22 FAMILY 31.5 31.5.1 AC (Timing) Characteristics TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2.
PIC18F87K22 FAMILY 31.5.2 TIMING CONDITIONS The temperature and voltages specified in Table 31-5 apply to all timing specifications unless otherwise noted. Figure 31-3 specifies the load conditions for the timing specifications.
PIC18F87K22 FAMILY 31.5.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 31-4: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 4 3 4 2 CLKO TABLE 31-6: Param. No. 1A EXTERNAL CLOCK TIMING REQUIREMENTS Symbol FOSC Characteristic External CLKIN Frequency(1) Oscillator Frequency(1) 1 TOSC Min Max Units Conditions DC 64 MHz DC 48 MHz -40°C ≤ TA ≤ +125°C DC 4 MHz RC Oscillator mode EC, ECIO Oscillator mode -40°C ≤ TA ≤ +85°C 0.
PIC18F87K22 FAMILY TABLE 31-7: Param No. PLL CLOCK TIMING SPECIFICATIONS (VDD = 1.8V TO 5.5V) Sym F10 Characteristic FOSC Oscillator Frequency Range F11 FSYS F12 F13 On-Chip VCO System Frequency Min Typ† Max Units 4 — 5 MHz VDD = 1.8-5.5V 4 — 16 MHz VDD = 3.0-5.5V, -40°C to +85°C 4 — 12 MHz VDD = 3.0-5.5V, -40°C to +125°C 16 — 20 MHz VDD = 1.8-5.5V 16 — 64 MHz VDD = 3.0-5.5V, -40°C to +85°C 16 — 48 MHz VDD = 3.0-5.
PIC18F87K22 FAMILY FIGURE 31-5: CLKO AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKO 13 14 19 12 18 16 I/O pin (Input) 15 17 I/O pin (Output) New Value Old Value 20, 21 Refer to Figure 31-3 for load conditions. Note: TABLE 31-9: Param No.
PIC18F87K22 FAMILY FIGURE 31-6: PROGRAM MEMORY FETCH TIMING DIAGRAM (8-BIT) Q1 Q2 Q3 Q4 Q1 Q2 OSC1 A<19:8> Address Address 167 166 150 161 151 AD<7:0> Data Data Address Address 162 153 162A 154 155 BA0 163 170 170A ALE 168 CE OE Note: Fmax = 25 MHz in 8-Bit External Memory mode. TABLE 31-10: PROGRAM MEMORY FETCH TIMING REQUIREMENTS (8-BIT) Param No 150 Symbol TadV2aIL Characteristics Address Out Valid to ALE (address setup time) Min Typ Max Units 0.
PIC18F87K22 FAMILY FIGURE 31-7: PROGRAM MEMORY READ TIMING DIAGRAM Q1 Q2 Q3 Q4 Q1 Q2 OSC1 A<19:16> BA0 Address Address Address AD<15:0> Data from External 150 151 Address 163 160 162 161 155 166 167 168 ALE 164 171 169 CE 171A OE 165 Operating Conditions: 2.0V < VCC < 3.6V, -40°C < TA < +125°C unless otherwise stated. TABLE 31-11: CLKO AND I/O TIMING REQUIREMENTS Param.
PIC18F87K22 FAMILY FIGURE 31-8: PROGRAM MEMORY WRITE TIMING DIAGRAM Q1 Q2 Q3 Q4 Q1 Q2 OSC1 A<19:16> BA0 Address Address 166 AD<15:0> Data Address Address 153 150 156 151 ALE 171 CE 171A 154 WRH or WRL 157A 157 UB or LB Operating Conditions: 2.0V < VCC < 3.6V, -40°C < TA < +125°C unless otherwise stated. TABLE 31-12: PROGRAM MEMORY WRITE TIMING REQUIREMENTS Param. No Symbol Characteristics Min Typ Max Units 150 TadV2alL Address Out Valid to ALE (address setup time) 0.
PIC18F87K22 FAMILY FIGURE 31-9: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 Oscillator Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O Pins Note: Refer to Figure 31-3 for load conditions. FIGURE 31-10: BROWN-OUT RESET TIMING VDD BVDD 35 VBGAP = 1.2V VIRVST Enable Internal Reference Voltage Internal Reference Voltage Stable 2011 Microchip Technology Inc.
PIC18F87K22 FAMILY TABLE 31-13: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param. Symbol No. Characteristic Min Typ Max Units 30 TmcL MCLR Pulse Width (low) 2 — — s 31 TWDT Watchdog Timer Time-out Period (no postscaler) — 4.00 — ms 32 TOST Oscillation Start-up Timer Period 1024 TOSC — 1024 TOSC — 33 TPWRT Power-up Timer Period — 65.
PIC18F87K22 FAMILY FIGURE 31-11: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS For VDIRMAG = 1: VDD VHLVD (HLVDIF set by hardware) (HLVDIF can be cleared in software) VHLVD For VDIRMAG = 0: VDD HLVDIF TABLE 31-14: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param Sym No.
PIC18F87K22 FAMILY FIGURE 31-12: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 41 40 42 T1CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 31-3 for load conditions. TABLE 31-15: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param No.
PIC18F87K22 FAMILY FIGURE 31-13: CAPTURE/COMPARE/PWM TIMINGS (ECCP1, ECCP2 MODULES) CCPx (Capture Mode) 50 51 52 CCPx (Compare or PWM Mode) 53 Note: 54 Refer to Figure 31-3 for load conditions. TABLE 31-16: CAPTURE/COMPARE/PWM REQUIREMENTS (ECCP1, ECCP2 MODULES) Param Symbol No. 50 51 TCCL TCCH Characteristic Min Max Units CCPx Input Low No prescaler Time With prescaler 0.5 TCY + 20 — ns 10 — ns CCPx Input High Time 0.
PIC18F87K22 FAMILY FIGURE 31-14: EXAMPLE SPI MASTER MODE TIMING (CKE = 0) SCKx (CKPx = 0) 78 79 79 78 SCKx (CKPx = 1) 80 bit 6 - - - - - - 1 MSb SDOx LSb 75, 76 SDIx MSb In bit 6 - - - - 1 LSb In 74 73 Note: Refer to Figure 31-3 for load conditions. TABLE 31-17: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0) Param No.
PIC18F87K22 FAMILY FIGURE 31-15: EXAMPLE SPI MASTER MODE TIMING (CKE = 1) 81 SCKx (CKPx = 0) 79 73 SCKx (CKPx = 1) 80 78 MSb SDOx bit 6 - - - - - - 1 LSb bit 6 - - - - 1 LSb In 75, 76 SDIx MSb In 74 Note: Refer to Figure 31-3 for load conditions. TABLE 31-18: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1) Param. No.
PIC18F87K22 FAMILY FIGURE 31-16: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0) SSx 70 SCKx (CKPx = 0) 83 71 72 78 79 79 78 SCKx (CKP = 1) 80 MSb SDOx bit 6 - - - - - - 1 LSb 75, 76 MSb In SDIx 77 bit 6 - - - - 1 LSb In 74 73 Refer to Figure 31-3 for load conditions. Note: TABLE 31-19: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0) Param No.
PIC18F87K22 FAMILY FIGURE 31-17: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1) 82 SSx SCKx (CKPx = 0) 70 83 71 72 SCKx (CKPx = 1) 80 MSb SDOx bit 6 - - - - - - 1 LSb 75, 76 SDIx MSb In 77 bit 6 - - - - 1 LSb In 74 Note: Refer to Figure 31-3 for load conditions. TABLE 31-20: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1) Param No.
PIC18F87K22 FAMILY I2C™ BUS START/STOP BITS TIMING FIGURE 31-18: SCLx 91 93 90 92 SDAx Stop Condition Start Condition Note: Refer to Figure 31-3 for load conditions. TABLE 31-21: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol No.
PIC18F87K22 FAMILY FIGURE 31-19: I2C™ BUS DATA TIMING 103 102 100 101 SCLx 90 106 107 91 92 SDAx In 110 109 109 SDAx Out Note: Refer to Figure 31-3 for load conditions. TABLE 31-22: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE) Param. No. 100 Symbol THIGH 101 TLOW 102 TR Characteristic Clock High Time Clock Low Time 100 kHz mode TF TSU:STA Units 4.0 — s s 0.6 — MSSP module 1.5 TCY — 100 kHz mode 4.7 — s 400 kHz mode 1.3 — s MSSP module 1.
PIC18F87K22 FAMILY MSSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS FIGURE 31-20: SCLx 93 91 90 92 SDAx Stop Condition Start Condition Note: Refer to Figure 31-3 for load conditions. TABLE 31-23: MSSP I2C™ BUS START/STOP BITS REQUIREMENTS Param. Symbol No.
PIC18F87K22 FAMILY TABLE 31-24: MSSP I2C™ BUS DATA REQUIREMENTS Param. Symbol No.
PIC18F87K22 FAMILY FIGURE 31-22: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING TXx/CKx Pin 121 121 RXx/DTx Pin 120 Note: 122 Refer to Figure 31-3 for load conditions. TABLE 31-25: EUSART/AUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param No.
PIC18F87K22 FAMILY TABLE 31-27: A/D CONVERTER CHARACTERISTICS: PIC18F87K22 FAMILY (INDUSTRIAL) Param No. Sym Characteristic Min Typ Max Units Conditions A01 NR Resolution — — 12 bit VREF 5.0V A03 EIL Integral Linearity Error — ±1 ±6.0 LSB VREF = 5.0V A04 EDL Differential Linearity Error — ±1 +3.0/-1.0 LSB VREF = 5.0V A06 EOFF Offset Error — ±1 ±9.0 LSB VREF = 5.0V A07 EGN Gain Error — ±1 ±8.0 LSB VREF = 5.
PIC18F87K22 FAMILY FIGURE 31-24: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) 131 Q4 130 132 A/D CLK 11 A/D DATA 10 9 ... ... 2 1 0 NEW_DATA OLD_DATA ADRES TCY (Note 1) ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
PIC18F87K22 FAMILY 32.0 PACKAGING INFORMATION 32.1 Package Marking Information 64-Lead TQFP Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 64-Lead QFN Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN e3 * Note: 18F67K22 -I/MR e3 1110017 Example 80-Lead TQFP Legend: XX...
PIC18F87K22 FAMILY 32.2 Package Details The following sections give the technical details of the packages.
PIC18F87K22 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2009-2011 Microchip Technology Inc.
PIC18F87K22 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS39960D-page 528 2009-2011 Microchip Technology Inc.
PIC18F87K22 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2009-2011 Microchip Technology Inc.
PIC18F87K22 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS39960D-page 530 2009-2011 Microchip Technology Inc.
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PIC18F87K22 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS39960D-page 532 2009-2011 Microchip Technology Inc.
PIC18F87K22 FAMILY APPENDIX A: REVISION HISTORY Revision A (November 2009) Original data sheet for PIC18F87K22 family devices. Revision B (May 2010) Minor edits to text throughout document. Replaced all TBDs with the correct value. Revision C (March 2011) Section 2.4 “Voltage Regulator Pins (ENVREG and VCAP/VDDCORE)” has been replaced with a new and more detailed description and the 80-pin TQFP diagrams have been updated. Minor text edits throughout document. Revision D (June 2011) Updated Section 31.
PIC18F87K22 FAMILY APPENDIX B: MIGRATION FROM PIC18F87J11 AND PIC18F8722 TO PIC18F87K22 Devices in the PIC18F87K22, PIC18F87J11 and PIC18F8722 families are similar in their functions and features. Code can be migrated from the other families to the PIC18F87K22 without many changes. The differences between the device families are listed in Table B-1.
PIC18F87K22 FAMILY INDEX A A/D .................................................................................... 351 Acquisition Requirements ......................................... 362 Analog Port Pins, Configuring................................... 363 Associated Registers ................................................ 366 Automatic Acquisition Time, Selecting and Configuring ....................................................... 363 Configuring the Module..........................................
PIC18F87K22 FAMILY BNZ ................................................................................... 442 BOR. See Brown-out Reset. BOV................................................................................... 445 BRA................................................................................... 443 Break Character (12-Bit) Transmit and Receive ............... 344 BRG. See Baud Rate Generator. Brown-out Reset (BOR) ...................................................... 75 Detecting .......
PIC18F87K22 FAMILY Core Features Easy Migration ............................................................ 10 Extended Instruction Set............................................... 9 External Memory Bus (EMB) ........................................ 9 Memory Options............................................................ 9 nanoWatt Technology ................................................... 9 Oscillator Options and Features ................................... 9 CPFSEQ .............................
PIC18F87K22 FAMILY Synchronous Master Mode ....................................... 345 Associated Registers, Receive ......................... 348 Associated Registers, Transmit ........................ 346 Reception.......................................................... 347 Reception Sequence......................................... 347 Transmission..................................................... 345 Transmission Sequence ................................... 345 Synchronous Slave Mode ..............
PIC18F87K22 FAMILY Operation .................................................................. 296 Read/Write Bit Information (R/W Bit) ................ 296, 299 Registers................................................................... 291 Serial Clock (RC3/SCKx/SCLx) ................................ 299 Slave Mode ............................................................... 296 Address Masking Modes 5-Bit .......................................................... 297 7-Bit ..........................
PIC18F87K22 FAMILY Interrupt Sources............................................................... 403 A/D Conversion Complete ........................................ 361 Capture Complete (CCP) .......................................... 251 Capture Complete (ECCP) ....................................... 263 Compare Complete (CCP) ........................................ 252 Compare Complete (ECCP) ..................................... 264 Interrupt-on-Change (RB7:RB4) ...............................
PIC18F87K22 FAMILY RD0/PSP0/CTPLS/AD0 .............................................. 28 RD1/PSP1/T5CKI/T7G ............................................... 19 RD1/T5CKI/T7G/PSP1/AD1 ....................................... 28 RD2/PSP2................................................................... 19 RD2/PSP2/AD2........................................................... 28 RD3/PSP3................................................................... 19 RD3/PSP3/AD3...........................................
PIC18F87K22 FAMILY Power-Managed Modes ...................................................... 57 and EUSART Operation............................................ 331 and PWM Operation ................................................. 279 and SPI Operation .................................................... 289 Clock Transitions and Status Indicators...................... 58 Entering....................................................................... 57 Exiting Idle and Sleep Modes ......................
PIC18F87K22 FAMILY CONFIG3H (Configuration 3 High) ........................... 410 CONFIG3L (Configuration 3 Low)............................. 409 CONFIG4L (Configuration 4 Low)............................. 411 CONFIG5H (Configuration 5 High) ........................... 413 CONFIG5L (Configuration 5 Low)............................. 412 CONFIG6H (Configuration 6 High) ........................... 415 CONFIG6L (Configuration 6 Low)............................. 414 CONFIG7H (Configuration 7 High) .............
PIC18F87K22 FAMILY Operation .................................................................. 237 Calibration......................................................... 240 Clock Source..................................................... 238 Digit Carry Rules............................................... 238 General Functionality ........................................ 239 Leap Year ......................................................... 239 Register Mapping.............................................
PIC18F87K22 FAMILY Timer4/6/8/10/12 ............................................................... 223 Associated Registers ................................................ 225 Interrupt..................................................................... 224 Operation .................................................................. 223 Output ....................................................................... 224 Postscaler. See Postscaler, Timer4/6/8/10/12. Prescaler.
PIC18F87K22 FAMILY Transition for Two-Speed Start-up (INTOSC to HSPLL).......................................... 423 Transition for Wake from Idle to Run Mode ................ 63 Transition for Wake from Sleep (HSPLL).................... 62 Transition from RC_RUN Mode to PRI_RUN Mode .................................................. 61 Transition from SEC_RUN Mode to PRI_RUN Mode (HSPLL) ................................... 59 Transition to RC_RUN Mode ......................................
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PIC18F87K22 FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO.
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