Datasheet
Table Of Contents
- LCD Driver and Keypad Interface Features:
- Low-Power Features:
- Flexible Oscillator Structure:
- Peripheral Highlights:
- Special Microcontroller Features:
- Special Microcontroller Features (Continued):
- Pin Diagrams – PIC18F6XJ90
- Pin Diagrams – PIC18F8XJ90
- Table of Contents
- Most Current Data Sheet
- Errata
- Customer Notification System
- 1.0 Device Overview
- 1.1 Core Features
- 1.2 LCD Driver
- 1.3 Other Special Features
- 1.4 Details on Individual Family Members
- TABLE 1-1: Device Features for the PIC18F6XJ90 (64-pin Devices)
- TABLE 1-2: Device Features for the PIC18F8XJ90 (80-pin Devices)
- FIGURE 1-1: PIC18F6XJ90 (64-pin) Block Diagram
- FIGURE 1-2: PIC18F8XJ90 (80-pin) Block Diagram
- TABLE 1-3: PIC18F6XJ90 Pinout I/O Descriptions
- TABLE 1-4: PIC18F8XJ90 Pinout I/O Descriptions
- 2.0 Guidelines for Getting Started with PIC18FJ Microcontrollers
- 3.0 Oscillator Configurations
- 3.1 Oscillator Types
- 3.2 Control Registers
- 3.3 Clock Sources and Oscillator Switching
- 3.4 External Oscillator Modes
- 3.5 Internal Oscillator Block
- 3.6 Effects of Power-Managed Modes on the Various Clock Sources
- 3.7 Power-up Delays
- 4.0 Power-Managed Modes
- 5.0 Reset
- 6.0 Memory Organization
- 6.1 Program Memory Organization
- 6.2 PIC18 Instruction Cycle
- 6.3 Data Memory Organization
- 6.4 Data Addressing Modes
- 6.5 Program Memory and the Extended Instruction Set
- 6.6 Data Memory and the Extended Instruction Set
- 7.0 Flash Program Memory
- 7.1 Table Reads and Table Writes
- 7.2 Control Registers
- 7.3 Reading the Flash Program Memory
- 7.4 Erasing Flash Program Memory
- 7.5 Writing to Flash Program Memory
- 7.6 Flash Program Operation During Code Protection
- 8.0 8 X 8 Hardware Multiplier
- 8.1 Introduction
- 8.2 Operation
- EXAMPLE 8-1: 8 x 8 Unsigned Multiply Routine
- EXAMPLE 8-2: 8 x 8 Signed Multiply Routine
- TABLE 8-1: Performance Comparison for Various Multiply Operations
- EQUATION 8-1: 16 x 16 Unsigned Multiplication Algorithm
- EXAMPLE 8-3: 16 x 16 Unsigned Multiply Routine
- EQUATION 8-2: 16 x 16 Signed Multiplication Algorithm
- EXAMPLE 8-4: 16 x 16 Signed Multiply Routine
- 9.0 Interrupts
- 10.0 I/O Ports
- FIGURE 10-1: Generic I/O Port Operation
- 10.1 I/O Port Pin Capabilities
- 10.2 PORTA, TRISA and LATA Registers
- 10.3 PORTB, TRISB and LATB Registers
- 10.4 PORTC, TRISC and LATC Registers
- 10.5 PORTD, TRISD and LATD Registers
- 10.6 PORTE, TRISE and LATE Registers
- 10.7 PORTF, LATF and TRISF Registers
- 10.8 PORTG, TRISG and LATG Registers
- 10.9 PORTH, LATH and TRISH Registers
- 10.10 PORTJ, TRISJ and LATJ Registers
- 11.0 Timer0 Module
- 12.0 Timer1 Module
- 13.0 Timer2 Module
- 14.0 Timer3 Module
- 15.0 Real-Time Clock and Calendar (RTCC)
- FIGURE 15-1: RTCC Block Diagram
- 15.1 RTCC Module Registers
- RTCC Control Registers
- RTCC Value Registers
- Alarm Value Registers
- 15.1.1 RTCC Control Registers
- 15.1.2 RTCVALH and RTCVALL Register Mappings
- Register 15-6: Reserved Register
- Register 15-7: Year: Year Value Register(1)
- Register 15-8: MontH: Month Value Register(1)
- Register 15-9: Day: Day Value Register(1)
- Register 15-10: Weekday: Weekday Value Register(1)
- Register 15-11: Hour: Hour Value Register(1)
- Register 15-12: MINUTE: Minute Value Register
- Register 15-13: SECOND: Second Value Register
- 15.1.3 ALRMVALH and ALRMVALL Register Mappings
- Register 15-14: ALRMMNTH: Alarm Month Value Register(1)
- Register 15-15: ALRMDAY: Alarm Day Value Register(1)
- Register 15-16: ALRMWd: Alarm Weekday Value Register(1)
- Register 15-17: ALRMHr: Alarm Hours Value Register(1)
- Register 15-18: ALRMMIN: Alarm Minutes Value Register
- Register 15-19: ALRMSEC: Alarm Seconds Value Register
- 15.1.4 RTCEN Bit Write
- 15.2 Operation
- 15.3 Alarm
- 15.4 Sleep Mode
- 15.5 Reset
- 15.6 Register Maps
- 16.0 Capture/Compare/PWM (CCP) Modules
- 17.0 Liquid Crystal Display (LCD) Driver Module
- FIGURE 17-1: LCD Driver Module Block Diagram
- 17.1 LCD Registers
- 17.2 LCD Clock Source
- 17.3 LCD Bias Generation
- 17.4 LCD Multiplex Types
- 17.5 Segment Enables
- 17.6 Pixel Control
- 17.7 LCD Frame Frequency
- 17.8 LCD Waveform Generation
- FIGURE 17-6: Type-A/Type-B Waveforms in Static Drive
- FIGURE 17-7: Type-A Waveforms in 1/2 MUX, 1/2 Bias Drive
- FIGURE 17-8: Type-B Waveforms in 1/2 MUX, 1/2 Bias Drive
- FIGURE 17-9: Type-A Waveforms in 1/2 MUX, 1/3 Bias Drive
- FIGURE 17-10: Type-B Waveforms in 1/2 MUX, 1/3 Bias Drive
- FIGURE 17-11: Type-A Waveforms in 1/3 MUX, 1/2 Bias Drive
- FIGURE 17-12: Type-B Waveforms in 1/3 MUX, 1/2 Bias Drive
- FIGURE 17-13: Type-A Waveforms in 1/3 MUX, 1/3 Bias Drive
- FIGURE 17-14: Type-B Waveforms in 1/3 MUX, 1/3 Bias Drive
- FIGURE 17-15: Type-A Waveforms in 1/4 MUX, 1/3 Bias Drive
- FIGURE 17-16: Type-B Waveforms in 1/4 MUX, 1/3 Bias Drive
- 17.9 LCD Interrupts
- 17.10 Operation During Sleep
- 17.11 Configuring the LCD Module
- 18.0 Master Synchronous Serial Port (MSSP) Module
- 18.1 Master SSP (MSSP) Module Overview
- 18.2 Control Registers
- 18.3 SPI Mode
- FIGURE 18-1: MSSP Block Diagram (SPI Mode)
- 18.3.1 Registers
- 18.3.2 Operation
- 18.3.3 Enabling SPI I/O
- 18.3.4 Open-Drain Output Option
- 18.3.5 Typical Connection
- 18.3.6 Master Mode
- 18.3.7 Slave Mode
- 18.3.8 Slave Select Synchronization
- 18.3.9 Operation in Power-Managed Modes
- 18.3.10 Effects of a Reset
- 18.3.11 Bus Mode Compatibility
- 18.4 I2C Mode
- FIGURE 18-7: MSSP Block Diagram (I2C™ Mode)
- 18.4.1 Registers
- 18.4.2 Operation
- 18.4.3 Slave Mode
- EXAMPLE 18-2: Address Masking Examples
- FIGURE 18-8: I2C™ Slave Mode Timing with SEN = 0 (Reception, 7-bit Addressing)
- FIGURE 18-9: I2C™ Slave Mode Timing with SEN = 0 and ADMSK<5:1> = 01011 (Reception, 7-bit Addressing)
- FIGURE 18-10: I2C™ Slave Mode Timing (Transmission, 7-bit Addressing)
- FIGURE 18-11: I2C™ Slave Mode Timing with SEN = 0 (Reception, 10-bit Addressing)
- FIGURE 18-12: I2C™ Slave Mode Timing with SEN = 0 and ADMSK<5:1> = 01001 (Reception, 10-bit Addressing)
- FIGURE 18-13: I2C™ Slave Mode Timing (Transmission, 10-bit Addressing)
- 18.4.4 Clock Stretching
- 18.4.5 General Call Address Support
- 18.4.6 Master Mode
- 18.4.7 Baud Rate
- 18.4.8 I2C Master Mode Start Condition Timing
- 18.4.9 I2C Master Mode Repeated Start Condition Timing
- 18.4.10 I2C Master Mode Transmission
- 18.4.11 I2C Master Mode Reception
- 18.4.12 Acknowledge Sequence Timing
- 18.4.13 Stop Condition Timing
- 18.4.14 Sleep Operation
- 18.4.15 Effects of a Reset
- 18.4.16 Multi-Master Mode
- 18.4.17 Multi -Master Communication, Bus Collision and Bus Arbitration
- FIGURE 18-27: Bus Collision Timing for Transmit and Acknowledge
- FIGURE 18-28: Bus Collision During Start Condition (SDA Only)
- FIGURE 18-29: Bus Collision During Start Condition (SCL = 0)
- FIGURE 18-30: BRG Reset Due to SDA Arbitration During Start Condition
- FIGURE 18-31: Bus Collision During a Repeated Start Condition (Case 1)
- FIGURE 18-32: Bus Collision During Repeated Start Condition (Case 2)
- FIGURE 18-33: Bus Collision During a Stop Condition (Case 1)
- FIGURE 18-34: Bus Collision During a Stop Condition (Case 2)
- TABLE 18-4: Registers Associated with I2C™ Operation
- 19.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)
- 19.1 Control Registers
- 19.2 EUSART Baud Rate Generator (BRG)
- 19.3 EUSART Asynchronous Mode
- 19.4 EUSART Synchronous Master Mode
- 19.5 EUSART Synchronous Slave Mode
- 20.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART)
- 20.1 Control Registers
- 20.2 AUSART Baud Rate Generator (BRG)
- 20.3 AUSART Asynchronous Mode
- 20.4 AUSART Synchronous Master Mode
- 20.5 AUSART Synchronous Slave Mode
- 21.0 10-Bit Analog-to-Digital Converter (A/D) Module
- Register 21-1: ADCON0: A/D Control Register 0
- Register 21-2: ADCON1: A/D Control Register 1
- Register 21-3: ADCON2: A/D Control Register 2
- FIGURE 21-1: A/D Block Diagram(1,2)
- FIGURE 21-2: Analog Input Model
- 21.1 A/D Acquisition Requirements
- 21.2 Selecting and Configuring Automatic Acquisition Time
- 21.3 Selecting the A/D Conversion Clock
- 21.4 Configuring Analog Port Pins
- 21.5 A/D Conversions
- 21.6 Use of the CCP2 Trigger
- 21.7 A/D Converter Calibration
- 21.8 Operation in Power-Managed Modes
- 22.0 Comparator Module
- Register 22-1: CMCON: Comparator Module Control Register
- 22.1 Comparator Configuration
- 22.2 Comparator Operation
- 22.3 Comparator Reference
- 22.4 Comparator Response Time
- 22.5 Comparator Outputs
- 22.6 Comparator Interrupts
- 22.7 Comparator Operation During Sleep
- 22.8 Effects of a Reset
- 22.9 Analog Input Connection Considerations
- 23.0 Comparator Voltage Reference Module
- 24.0 Charge Time Measurement Unit (CTMU)
- FIGURE 24-1: CTMU Block Diagram
- 24.1 CTMU Operation
- 24.2 CTMU Module Initialization
- 24.3 Calibrating the CTMU Module
- 24.4 Measuring Capacitance with the CTMU
- 24.5 Measuring Time with the CTMU Module
- 24.6 Creating a Delay with the CTMU Module
- 24.7 Operation During Sleep/Idle Modes
- 24.8 Effects of a Reset on CTMU
- 24.9 Registers
- 25.0 Special Features of the CPU
- 25.1 Configuration Bits
- 25.1.1 Considerations for Configuring PIC18F87J90 Family Devices
- TABLE 25-1: Mapping of the Flash Configuration Words to the Configuration Registers
- TABLE 25-2: Configuration Bits and Device IDs
- Register 25-1: CONFIG1L: Configuration Register 1 Low (Byte Address 300000h)
- Register 25-2: CONFIG1H: Configuration Register 1 High (Byte Address 300001h)
- Register 25-3: CONFIG2L: Configuration Register 2 Low (Byte Address 300002h)
- Register 25-4: CONFIG2H: Configuration Register 2 High (Byte Address 300003h)
- Register 25-5: CONFIG3L: Configuration Register 3 Low (Byte Address 300004h)
- Register 25-6: CONFIG3H: Configuration Register 3 High (Byte Address 300005h)
- Register 25-7: DEVID1: Device ID Register 1 for PIC18F87J90 Family Devices
- Register 25-8: DEVID2: Device ID Register 2 for PIC18F87J90 Family Devices
- 25.1.1 Considerations for Configuring PIC18F87J90 Family Devices
- 25.2 Watchdog Timer (WDT)
- 25.3 On-Chip Voltage Regulator
- 25.4 Two-Speed Start-up
- 25.5 Fail-Safe Clock Monitor
- 25.6 Program Verification and Code Protection
- 25.7 In-Circuit Serial Programming
- 25.8 In-Circuit Debugger
- 25.1 Configuration Bits
- 26.0 Instruction Set Summary
- 26.1 Standard Instruction Set
- 26.2 Extended Instruction Set
- 27.0 Development Support
- 27.1 MPLAB Integrated Development Environment Software
- 27.2 MPLAB C Compilers for Various Device Families
- 27.3 HI-TECH C for Various Device Families
- 27.4 MPASM Assembler
- 27.5 MPLINK Object Linker/ MPLIB Object Librarian
- 27.6 MPLAB Assembler, Linker and Librarian for Various Device Families
- 27.7 MPLAB SIM Software Simulator
- 27.8 MPLAB REAL ICE In-Circuit Emulator System
- 27.9 MPLAB ICD 3 In-Circuit Debugger System
- 27.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express
- 27.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express
- 27.12 MPLAB PM3 Device Programmer
- 27.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits
- 28.0 Electrical Characteristics
- Absolute Maximum Ratings(†)
- 28.1 DC Characteristics: Supply Voltage PIC18F87J90 Family (Industrial)
- 28.2 DC Characteristics: Power-Down and Supply Current PIC18F87J90 Family (Industrial)
- 28.3 DC Characteristics: PIC18F87J90 Family (Industrial)
- 28.4 DC Characteristics: CTMU Current Source Specifications
- 28.5 AC (Timing) Characteristics
- 28.5.1 Timing Parameter Symbology
- 28.5.2 Timing Conditions
- 28.5.3 Timing Diagrams and Specifications
- FIGURE 28-4: External Clock Timing
- TABLE 28-7: External Clock Timing Requirements
- TABLE 28-8: PLL Clock Timing Specifications (Vdd = 2.15V to 3.6V)
- TABLE 28-9: Internal RC Accuracy (INTOSC and INTRC Sources)
- FIGURE 28-5: CLKO and I/O Timing
- TABLE 28-10: CLKO and I/O Timing Requirements
- FIGURE 28-6: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing
- TABLE 28-11: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements
- FIGURE 28-7: Timer0 and Timer1 External Clock Timings
- TABLE 28-12: Timer0 and Timer1 External Clock Requirements
- FIGURE 28-8: Capture/Compare/PWM Timings (CCP1, CCP2 Modules)
- TABLE 28-13: Capture/Compare/PWM Requirements (CCP1, CCP2 Modules)
- FIGURE 28-9: Example SPI Master Mode Timing (CKE = 0)
- TABLE 28-14: Example SPI Mode Requirements (Master Mode, Cke = 0)
- FIGURE 28-10: Example SPI Master Mode Timing (CKE = 1)
- TABLE 28-15: Example SPI Mode Requirements (Master Mode, CKE = 1)
- FIGURE 28-11: Example SPI Slave Mode Timing (CKE = 0)
- TABLE 28-16: Example SPI Mode Requirements (Slave Mode Timing, CKE = 0)
- FIGURE 28-12: Example SPI Slave Mode Timing (CKE = 1)
- TABLE 28-17: Example SPI Slave Mode Requirements (CKE = 1)
- FIGURE 28-13: I2C™ Bus Start/Stop Bits Timing
- TABLE 28-18: I2C™ Bus Start/Stop Bits Requirements (Slave Mode)
- FIGURE 28-14: I2C™ Bus Data Timing
- TABLE 28-19: I2C™ Bus Data Requirements (Slave Mode)
- FIGURE 28-15: MSSP I2C™ Bus Start/Stop Bits Timing Waveforms
- TABLE 28-20: MSSP I2C™ Bus Start/Stop Bits Requirements
- FIGURE 28-16: MSSP I2C™ Bus Data Timing
- TABLE 28-21: MSSP I2C™ Bus Data Requirements
- FIGURE 28-17: EUSART/AUSART Synchronous Transmission (Master/Slave) Timing
- TABLE 28-22: EUSART/AUSART Synchronous Transmission Requirements
- FIGURE 28-18: EUSART/AUSART Synchronous Receive (Master/Slave) Timing
- TABLE 28-23: EUSART/AUSART Synchronous Receive Requirements
- TABLE 28-24: A/D Converter Characteristics: PIC18F87J90 Family (Industrial)
- FIGURE 28-19: A/D Conversion Timing
- TABLE 28-25: A/D Conversion Requirements
- 29.0 Packaging Information
- Appendix A: Revision History
- Appendix B: Migration From PIC18F85J90 to PIC18F87J90
- INDEX
- The Microchip Web Site
- Customer Change Notification Service
- Customer Support
- Reader Response
- Product Identification System
- Worldwide Sales and Service
2010 Microchip Technology Inc. DS39933D-page 79
PIC18F87J90 FAMILY
PORTJ
(2)
RJ7RJ6RJ5RJ4RJ3RJ2RJ1RJ0
xxxx xxxx
62, 138
PORTH
(2)
RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0
xxxx xxxx
62, 136
PORTG RDPU REPU RJPU
(2)
RG4RG3RG2RG1RG0
000x xxxx
62, 134
PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1
—
xxxx xxx-
62, 132
PORTE RE7 RE6 RE5 RE4 RE3
—RE1RE0
xxxx x-xx
63, 129
PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0
xxxx xxxx
63, 127
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0
xxxx xxxx
63, 125
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0
xxxx xxxx
63, 122
PORTA RA7
(5)
RA6
(5)
RA5RA4RA3RA2RA1RA0
xx0x 0000
63, 119
SPBRGH1 EUSART Baud Rate Generator High Byte
0000 0000
63, 259
BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16
—WUEABDEN
0100 0-00
63, 258
LCDDATA23
(2)
S47C3 S46C3 S45C3 S44C3 S43C3 S42C3 S41C3 S40C3
xxxx xxxx
63, 187
LCDDATA22 S39C3
(2)
S38C3
(2)
S37C3
(2)
S36C3
(2)
S35C3
(2)
S34C3
(2)
S33C3
(2)
S32C3
xxxx xxxx
63, 187
LCDDATA21 S31C3 S30C3 S29C3 S28C3 S27C3 S26C3 S25C3 S24C3
xxxx xxxx
63, 187
LCDDATA20 S23C3 S22C3 S21C3 S20C3 S19C3 S18C3 S17C3 S16C3
xxxx xxxx
63, 187
LCDDATA19 S15C3 S14C3 S13C3 S12C3 S11C3 S10C3 S09C3 S08C3
xxxx xxxx
63, 187
LCDDATA18 S07C3 S06C3 S05C3 S04C3 S03C3 S02C3 S01C3 S00C3
xxxx xxxx
63, 187
LCDDATA17
(2)
S47C2 S46C2 S45C2 S44C2 S43C2 S42C2 S41C2 S40C2
xxxx xxxx
63, 187
LCDDATA16 S39C2
(2)
S38C2
(2)
S37C2
(2)
S36C2
(2)
S35C2
(2)
S34C2
(2)
S33C2
(2)
S32C2
xxxx xxxx
63, 187
LCDDATA15 S31C2 S30C2 S29C2 S28C2 S27C2 S26C2 S25C2 S24C2
xxxx xxxx
63, 187
LCDDATA14 S23C2 S22C2 S21C2 S20C2 S19C2 S18C2 S17C2 S16C2
xxxx xxxx
63, 187
LCDDATA13 S15C2 S14C2 S13C2 S12C2 S11C2 S10C2 S09C2 S08C2
xxxx xxxx
63, 187
LCDDATA12 S07C2 S06C2 S05C2 S04C2 S03C2 S02C2 S01C2 S00C2
xxxx xxxx
63, 187
LCDDATA11
(2)
S47C1 S46C1 S45C1 S44C1 S43C1 S42C1 S41C1 S40C1
xxxx xxxx
63, 187
LCDDATA10 S39C1
(2)
S38C1
(2)
S37C1
(2)
S36C1
(2)
S35C1
(2)
S34C1
(2)
S33C1
(2)
S32C1
xxxx xxxx
63, 187
LCDDATA9 S31C1 S30C1 S29C1 S28C1 S27C1 S26C1 S25C1 S24C1
xxxx xxxx
63, 187
LCDDATA8 S23C1 S22C1 S21C1 S20C1 S19C1 S18C1 S17C1 S16C1
xxxx xxxx
63, 187
LCDDATA7 S15C1 S14C1 S13C1 S12C1 S11C1 S10C1 S09C1 S08C1
xxxx xxxx
63, 187
LCDDATA6 S07C1 S06C1 S05C1 S04C1 S03C1 S02C1 S01C1 S00C1
xxxx xxxx
63, 187
LCDDATA5
(2)
S47C0 S46C0 S45C0 S44C0 S43C0 S42C0 S41C0 S40C0
xxxx xxxx
63, 187
CCPR1H Capture/Compare/PWM Register 1 High Byte
xxxx xxxx
63, 174
CCPR1L Capture/Compare/PWM Register 1 Low Byte
xxxx xxxx
63, 174
CCP1CON
— — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0
--00 0000
63, 173
CCPR2H Capture/Compare/PWM Register 2 High Byte
xxxx xxxx
63, 174
CCPR2L Capture/Compare/PWM Register 2 Low Byte
xxxx xxxx
64, 174
CCP2CON
— — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0
--00 0000
64, 173
SPBRG2 AUSART Baud Rate Generator Register
0000 0000
64, 278
RCREG2 AUSART Receive Register
0000 0000
64, 283
TXREG2 AUSART Transmit Register
0000 0000
64, 281
TXSTA2 CSRC TX9 TXEN SYNC
— BRGH TRMT TX9D
0000 -010
64, 276
RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
0000 000x
64, 277
RTCCFG RTCEN
— RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR1 RTCPTR0
0-00 0000
64, 157
RTCCAL CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0
0000 0000
64, 158
RTCVALH RTCC Value High Register Window based on RTCPTR<1:0>
xxxx xxxx
64, 160
TABLE 6-3: PIC18F87J90 FAMILY REGISTER FILE SUMMARY (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details on
page
Legend:
x
= unknown,
u
= unchanged,
-
= unimplemented,
q
= value depends on condition,
r
= reserved, do not modify
Note 1:
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2:
These registers and/or bits are available only on 80-pin devices; otherwise, they are unimplemented and read as ‘
0
’. Reset states shown are
for 80-pin devices.
3:
Alternate names and definitions for these bits when the MSSP module is operating in I
2
C™ Slave mode. See
Section 18.4.3.2 “Address
Masking”
for details.
4:
The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘
0
’. See
Section 3.4.3 “PLL
Frequency Multiplier”
for details.
5:
RA<7:6> and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default
clock source (FOSC2 Configuration bit =
0
); otherwise, they are disabled and these bits read as ‘
0
’.