Datasheet
Table Of Contents
- LCD Driver and Keypad Interface Features:
- Low-Power Features:
- Flexible Oscillator Structure:
- Peripheral Highlights:
- Special Microcontroller Features:
- Special Microcontroller Features (Continued):
- Pin Diagrams – PIC18F6XJ90
- Pin Diagrams – PIC18F8XJ90
- Table of Contents
- Most Current Data Sheet
- Errata
- Customer Notification System
- 1.0 Device Overview
- 1.1 Core Features
- 1.2 LCD Driver
- 1.3 Other Special Features
- 1.4 Details on Individual Family Members
- TABLE 1-1: Device Features for the PIC18F6XJ90 (64-pin Devices)
- TABLE 1-2: Device Features for the PIC18F8XJ90 (80-pin Devices)
- FIGURE 1-1: PIC18F6XJ90 (64-pin) Block Diagram
- FIGURE 1-2: PIC18F8XJ90 (80-pin) Block Diagram
- TABLE 1-3: PIC18F6XJ90 Pinout I/O Descriptions
- TABLE 1-4: PIC18F8XJ90 Pinout I/O Descriptions
- 2.0 Guidelines for Getting Started with PIC18FJ Microcontrollers
- 3.0 Oscillator Configurations
- 3.1 Oscillator Types
- 3.2 Control Registers
- 3.3 Clock Sources and Oscillator Switching
- 3.4 External Oscillator Modes
- 3.5 Internal Oscillator Block
- 3.6 Effects of Power-Managed Modes on the Various Clock Sources
- 3.7 Power-up Delays
- 4.0 Power-Managed Modes
- 5.0 Reset
- 6.0 Memory Organization
- 6.1 Program Memory Organization
- 6.2 PIC18 Instruction Cycle
- 6.3 Data Memory Organization
- 6.4 Data Addressing Modes
- 6.5 Program Memory and the Extended Instruction Set
- 6.6 Data Memory and the Extended Instruction Set
- 7.0 Flash Program Memory
- 7.1 Table Reads and Table Writes
- 7.2 Control Registers
- 7.3 Reading the Flash Program Memory
- 7.4 Erasing Flash Program Memory
- 7.5 Writing to Flash Program Memory
- 7.6 Flash Program Operation During Code Protection
- 8.0 8 X 8 Hardware Multiplier
- 8.1 Introduction
- 8.2 Operation
- EXAMPLE 8-1: 8 x 8 Unsigned Multiply Routine
- EXAMPLE 8-2: 8 x 8 Signed Multiply Routine
- TABLE 8-1: Performance Comparison for Various Multiply Operations
- EQUATION 8-1: 16 x 16 Unsigned Multiplication Algorithm
- EXAMPLE 8-3: 16 x 16 Unsigned Multiply Routine
- EQUATION 8-2: 16 x 16 Signed Multiplication Algorithm
- EXAMPLE 8-4: 16 x 16 Signed Multiply Routine
- 9.0 Interrupts
- 10.0 I/O Ports
- FIGURE 10-1: Generic I/O Port Operation
- 10.1 I/O Port Pin Capabilities
- 10.2 PORTA, TRISA and LATA Registers
- 10.3 PORTB, TRISB and LATB Registers
- 10.4 PORTC, TRISC and LATC Registers
- 10.5 PORTD, TRISD and LATD Registers
- 10.6 PORTE, TRISE and LATE Registers
- 10.7 PORTF, LATF and TRISF Registers
- 10.8 PORTG, TRISG and LATG Registers
- 10.9 PORTH, LATH and TRISH Registers
- 10.10 PORTJ, TRISJ and LATJ Registers
- 11.0 Timer0 Module
- 12.0 Timer1 Module
- 13.0 Timer2 Module
- 14.0 Timer3 Module
- 15.0 Real-Time Clock and Calendar (RTCC)
- FIGURE 15-1: RTCC Block Diagram
- 15.1 RTCC Module Registers
- RTCC Control Registers
- RTCC Value Registers
- Alarm Value Registers
- 15.1.1 RTCC Control Registers
- 15.1.2 RTCVALH and RTCVALL Register Mappings
- Register 15-6: Reserved Register
- Register 15-7: Year: Year Value Register(1)
- Register 15-8: MontH: Month Value Register(1)
- Register 15-9: Day: Day Value Register(1)
- Register 15-10: Weekday: Weekday Value Register(1)
- Register 15-11: Hour: Hour Value Register(1)
- Register 15-12: MINUTE: Minute Value Register
- Register 15-13: SECOND: Second Value Register
- 15.1.3 ALRMVALH and ALRMVALL Register Mappings
- Register 15-14: ALRMMNTH: Alarm Month Value Register(1)
- Register 15-15: ALRMDAY: Alarm Day Value Register(1)
- Register 15-16: ALRMWd: Alarm Weekday Value Register(1)
- Register 15-17: ALRMHr: Alarm Hours Value Register(1)
- Register 15-18: ALRMMIN: Alarm Minutes Value Register
- Register 15-19: ALRMSEC: Alarm Seconds Value Register
- 15.1.4 RTCEN Bit Write
- 15.2 Operation
- 15.3 Alarm
- 15.4 Sleep Mode
- 15.5 Reset
- 15.6 Register Maps
- 16.0 Capture/Compare/PWM (CCP) Modules
- 17.0 Liquid Crystal Display (LCD) Driver Module
- FIGURE 17-1: LCD Driver Module Block Diagram
- 17.1 LCD Registers
- 17.2 LCD Clock Source
- 17.3 LCD Bias Generation
- 17.4 LCD Multiplex Types
- 17.5 Segment Enables
- 17.6 Pixel Control
- 17.7 LCD Frame Frequency
- 17.8 LCD Waveform Generation
- FIGURE 17-6: Type-A/Type-B Waveforms in Static Drive
- FIGURE 17-7: Type-A Waveforms in 1/2 MUX, 1/2 Bias Drive
- FIGURE 17-8: Type-B Waveforms in 1/2 MUX, 1/2 Bias Drive
- FIGURE 17-9: Type-A Waveforms in 1/2 MUX, 1/3 Bias Drive
- FIGURE 17-10: Type-B Waveforms in 1/2 MUX, 1/3 Bias Drive
- FIGURE 17-11: Type-A Waveforms in 1/3 MUX, 1/2 Bias Drive
- FIGURE 17-12: Type-B Waveforms in 1/3 MUX, 1/2 Bias Drive
- FIGURE 17-13: Type-A Waveforms in 1/3 MUX, 1/3 Bias Drive
- FIGURE 17-14: Type-B Waveforms in 1/3 MUX, 1/3 Bias Drive
- FIGURE 17-15: Type-A Waveforms in 1/4 MUX, 1/3 Bias Drive
- FIGURE 17-16: Type-B Waveforms in 1/4 MUX, 1/3 Bias Drive
- 17.9 LCD Interrupts
- 17.10 Operation During Sleep
- 17.11 Configuring the LCD Module
- 18.0 Master Synchronous Serial Port (MSSP) Module
- 18.1 Master SSP (MSSP) Module Overview
- 18.2 Control Registers
- 18.3 SPI Mode
- FIGURE 18-1: MSSP Block Diagram (SPI Mode)
- 18.3.1 Registers
- 18.3.2 Operation
- 18.3.3 Enabling SPI I/O
- 18.3.4 Open-Drain Output Option
- 18.3.5 Typical Connection
- 18.3.6 Master Mode
- 18.3.7 Slave Mode
- 18.3.8 Slave Select Synchronization
- 18.3.9 Operation in Power-Managed Modes
- 18.3.10 Effects of a Reset
- 18.3.11 Bus Mode Compatibility
- 18.4 I2C Mode
- FIGURE 18-7: MSSP Block Diagram (I2C™ Mode)
- 18.4.1 Registers
- 18.4.2 Operation
- 18.4.3 Slave Mode
- EXAMPLE 18-2: Address Masking Examples
- FIGURE 18-8: I2C™ Slave Mode Timing with SEN = 0 (Reception, 7-bit Addressing)
- FIGURE 18-9: I2C™ Slave Mode Timing with SEN = 0 and ADMSK<5:1> = 01011 (Reception, 7-bit Addressing)
- FIGURE 18-10: I2C™ Slave Mode Timing (Transmission, 7-bit Addressing)
- FIGURE 18-11: I2C™ Slave Mode Timing with SEN = 0 (Reception, 10-bit Addressing)
- FIGURE 18-12: I2C™ Slave Mode Timing with SEN = 0 and ADMSK<5:1> = 01001 (Reception, 10-bit Addressing)
- FIGURE 18-13: I2C™ Slave Mode Timing (Transmission, 10-bit Addressing)
- 18.4.4 Clock Stretching
- 18.4.5 General Call Address Support
- 18.4.6 Master Mode
- 18.4.7 Baud Rate
- 18.4.8 I2C Master Mode Start Condition Timing
- 18.4.9 I2C Master Mode Repeated Start Condition Timing
- 18.4.10 I2C Master Mode Transmission
- 18.4.11 I2C Master Mode Reception
- 18.4.12 Acknowledge Sequence Timing
- 18.4.13 Stop Condition Timing
- 18.4.14 Sleep Operation
- 18.4.15 Effects of a Reset
- 18.4.16 Multi-Master Mode
- 18.4.17 Multi -Master Communication, Bus Collision and Bus Arbitration
- FIGURE 18-27: Bus Collision Timing for Transmit and Acknowledge
- FIGURE 18-28: Bus Collision During Start Condition (SDA Only)
- FIGURE 18-29: Bus Collision During Start Condition (SCL = 0)
- FIGURE 18-30: BRG Reset Due to SDA Arbitration During Start Condition
- FIGURE 18-31: Bus Collision During a Repeated Start Condition (Case 1)
- FIGURE 18-32: Bus Collision During Repeated Start Condition (Case 2)
- FIGURE 18-33: Bus Collision During a Stop Condition (Case 1)
- FIGURE 18-34: Bus Collision During a Stop Condition (Case 2)
- TABLE 18-4: Registers Associated with I2C™ Operation
- 19.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)
- 19.1 Control Registers
- 19.2 EUSART Baud Rate Generator (BRG)
- 19.3 EUSART Asynchronous Mode
- 19.4 EUSART Synchronous Master Mode
- 19.5 EUSART Synchronous Slave Mode
- 20.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART)
- 20.1 Control Registers
- 20.2 AUSART Baud Rate Generator (BRG)
- 20.3 AUSART Asynchronous Mode
- 20.4 AUSART Synchronous Master Mode
- 20.5 AUSART Synchronous Slave Mode
- 21.0 10-Bit Analog-to-Digital Converter (A/D) Module
- Register 21-1: ADCON0: A/D Control Register 0
- Register 21-2: ADCON1: A/D Control Register 1
- Register 21-3: ADCON2: A/D Control Register 2
- FIGURE 21-1: A/D Block Diagram(1,2)
- FIGURE 21-2: Analog Input Model
- 21.1 A/D Acquisition Requirements
- 21.2 Selecting and Configuring Automatic Acquisition Time
- 21.3 Selecting the A/D Conversion Clock
- 21.4 Configuring Analog Port Pins
- 21.5 A/D Conversions
- 21.6 Use of the CCP2 Trigger
- 21.7 A/D Converter Calibration
- 21.8 Operation in Power-Managed Modes
- 22.0 Comparator Module
- Register 22-1: CMCON: Comparator Module Control Register
- 22.1 Comparator Configuration
- 22.2 Comparator Operation
- 22.3 Comparator Reference
- 22.4 Comparator Response Time
- 22.5 Comparator Outputs
- 22.6 Comparator Interrupts
- 22.7 Comparator Operation During Sleep
- 22.8 Effects of a Reset
- 22.9 Analog Input Connection Considerations
- 23.0 Comparator Voltage Reference Module
- 24.0 Charge Time Measurement Unit (CTMU)
- FIGURE 24-1: CTMU Block Diagram
- 24.1 CTMU Operation
- 24.2 CTMU Module Initialization
- 24.3 Calibrating the CTMU Module
- 24.4 Measuring Capacitance with the CTMU
- 24.5 Measuring Time with the CTMU Module
- 24.6 Creating a Delay with the CTMU Module
- 24.7 Operation During Sleep/Idle Modes
- 24.8 Effects of a Reset on CTMU
- 24.9 Registers
- 25.0 Special Features of the CPU
- 25.1 Configuration Bits
- 25.1.1 Considerations for Configuring PIC18F87J90 Family Devices
- TABLE 25-1: Mapping of the Flash Configuration Words to the Configuration Registers
- TABLE 25-2: Configuration Bits and Device IDs
- Register 25-1: CONFIG1L: Configuration Register 1 Low (Byte Address 300000h)
- Register 25-2: CONFIG1H: Configuration Register 1 High (Byte Address 300001h)
- Register 25-3: CONFIG2L: Configuration Register 2 Low (Byte Address 300002h)
- Register 25-4: CONFIG2H: Configuration Register 2 High (Byte Address 300003h)
- Register 25-5: CONFIG3L: Configuration Register 3 Low (Byte Address 300004h)
- Register 25-6: CONFIG3H: Configuration Register 3 High (Byte Address 300005h)
- Register 25-7: DEVID1: Device ID Register 1 for PIC18F87J90 Family Devices
- Register 25-8: DEVID2: Device ID Register 2 for PIC18F87J90 Family Devices
- 25.1.1 Considerations for Configuring PIC18F87J90 Family Devices
- 25.2 Watchdog Timer (WDT)
- 25.3 On-Chip Voltage Regulator
- 25.4 Two-Speed Start-up
- 25.5 Fail-Safe Clock Monitor
- 25.6 Program Verification and Code Protection
- 25.7 In-Circuit Serial Programming
- 25.8 In-Circuit Debugger
- 25.1 Configuration Bits
- 26.0 Instruction Set Summary
- 26.1 Standard Instruction Set
- 26.2 Extended Instruction Set
- 27.0 Development Support
- 27.1 MPLAB Integrated Development Environment Software
- 27.2 MPLAB C Compilers for Various Device Families
- 27.3 HI-TECH C for Various Device Families
- 27.4 MPASM Assembler
- 27.5 MPLINK Object Linker/ MPLIB Object Librarian
- 27.6 MPLAB Assembler, Linker and Librarian for Various Device Families
- 27.7 MPLAB SIM Software Simulator
- 27.8 MPLAB REAL ICE In-Circuit Emulator System
- 27.9 MPLAB ICD 3 In-Circuit Debugger System
- 27.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express
- 27.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express
- 27.12 MPLAB PM3 Device Programmer
- 27.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits
- 28.0 Electrical Characteristics
- Absolute Maximum Ratings(†)
- 28.1 DC Characteristics: Supply Voltage PIC18F87J90 Family (Industrial)
- 28.2 DC Characteristics: Power-Down and Supply Current PIC18F87J90 Family (Industrial)
- 28.3 DC Characteristics: PIC18F87J90 Family (Industrial)
- 28.4 DC Characteristics: CTMU Current Source Specifications
- 28.5 AC (Timing) Characteristics
- 28.5.1 Timing Parameter Symbology
- 28.5.2 Timing Conditions
- 28.5.3 Timing Diagrams and Specifications
- FIGURE 28-4: External Clock Timing
- TABLE 28-7: External Clock Timing Requirements
- TABLE 28-8: PLL Clock Timing Specifications (Vdd = 2.15V to 3.6V)
- TABLE 28-9: Internal RC Accuracy (INTOSC and INTRC Sources)
- FIGURE 28-5: CLKO and I/O Timing
- TABLE 28-10: CLKO and I/O Timing Requirements
- FIGURE 28-6: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing
- TABLE 28-11: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements
- FIGURE 28-7: Timer0 and Timer1 External Clock Timings
- TABLE 28-12: Timer0 and Timer1 External Clock Requirements
- FIGURE 28-8: Capture/Compare/PWM Timings (CCP1, CCP2 Modules)
- TABLE 28-13: Capture/Compare/PWM Requirements (CCP1, CCP2 Modules)
- FIGURE 28-9: Example SPI Master Mode Timing (CKE = 0)
- TABLE 28-14: Example SPI Mode Requirements (Master Mode, Cke = 0)
- FIGURE 28-10: Example SPI Master Mode Timing (CKE = 1)
- TABLE 28-15: Example SPI Mode Requirements (Master Mode, CKE = 1)
- FIGURE 28-11: Example SPI Slave Mode Timing (CKE = 0)
- TABLE 28-16: Example SPI Mode Requirements (Slave Mode Timing, CKE = 0)
- FIGURE 28-12: Example SPI Slave Mode Timing (CKE = 1)
- TABLE 28-17: Example SPI Slave Mode Requirements (CKE = 1)
- FIGURE 28-13: I2C™ Bus Start/Stop Bits Timing
- TABLE 28-18: I2C™ Bus Start/Stop Bits Requirements (Slave Mode)
- FIGURE 28-14: I2C™ Bus Data Timing
- TABLE 28-19: I2C™ Bus Data Requirements (Slave Mode)
- FIGURE 28-15: MSSP I2C™ Bus Start/Stop Bits Timing Waveforms
- TABLE 28-20: MSSP I2C™ Bus Start/Stop Bits Requirements
- FIGURE 28-16: MSSP I2C™ Bus Data Timing
- TABLE 28-21: MSSP I2C™ Bus Data Requirements
- FIGURE 28-17: EUSART/AUSART Synchronous Transmission (Master/Slave) Timing
- TABLE 28-22: EUSART/AUSART Synchronous Transmission Requirements
- FIGURE 28-18: EUSART/AUSART Synchronous Receive (Master/Slave) Timing
- TABLE 28-23: EUSART/AUSART Synchronous Receive Requirements
- TABLE 28-24: A/D Converter Characteristics: PIC18F87J90 Family (Industrial)
- FIGURE 28-19: A/D Conversion Timing
- TABLE 28-25: A/D Conversion Requirements
- 29.0 Packaging Information
- Appendix A: Revision History
- Appendix B: Migration From PIC18F85J90 to PIC18F87J90
- INDEX
- The Microchip Web Site
- Customer Change Notification Service
- Customer Support
- Reader Response
- Product Identification System
- Worldwide Sales and Service
2010 Microchip Technology Inc. DS39933D-page 267
PIC18F87J90 FAMILY
FIGURE 19-7: ASYNCHRONOUS RECEPTION
TABLE 19-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 59
PIR1 — ADIF RC1IF TX1IF SSPIF — TMR2IF TMR1IF 62
PIE1 — ADIE RC1IE TX1IE SSPIE — TMR2IE TMR1IE 62
IPR1
— ADIP RC1IP TX1IP SSPIP — TMR2IP TMR1IP 62
RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 61
RCREG1 EUSART Receive Register 61
TXSTA1
CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 61
BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 63
SPBRGH1 EUSART Baud Rate Generator Register High Byte 61
SPBRG1 EUSART Baud Rate Generator Register Low Byte 61
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Start
bit
bit 7/8
bit 1bit 0 bit 7/8
bit 0Stop
bit
Start
bit
Start
bit
bit 7/8
Stop
bit
RX1 (pin)
Rcv Buffer Reg
Rcv Shift Reg
Read Rcv
Buffer Reg
RCREG1
RC1IF
(Interrupt Flag)
OERR bit
CREN bit
Word 1
RCREG1
Word 2
RCREG1
Stop
bit
Note: This timing diagram shows three words appearing on the RX1 input. The RCREG1 (Receive Buffer register) is read after the third word
causing the OERR (Overrun) bit to be set.