Datasheet

 2007-2012 Microchip Technology Inc. DS39778E-page 85
PIC18F87J11 FAMILY
TRISJ
(7)
TRISJ7 TRISJ6 TRISJ5 TRISJ4 TRISJ3 TRISJ2 TRISJ1 TRISJ0 1111 1111 64, 165
TRISH
(7)
TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 1111 1111 64, 163
TRISG
— — — TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 ---1 1111 64, 160
TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1
— 1111 111- 64, 157
TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 1111 1111 64, 154
TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 64, 151
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 64, 148
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 64, 145
TRISA TRISA7
(8)
TRISA6
(8)
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 64, 142
LATJ
(7)
LATJ7 LATJ6 LATJ5 LATJ4 LATJ3 LATJ2 LATJ1 LATJ0 xxxx xxxx 64, 165
LATH
(7)
LATH7 LATH6 LATH5 LATH4 LATH3 LATH2 LATH1 LATH0 xxxx xxxx 64, 163
LATG
— — — LATG4 LATG3 LATG2 LATG1 LATG0 ---x xxxx 64, 160
LATF LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1
— xxxx xxx- 64, 157
LATE LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 xxxx xxxx 64, 154
LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx xxxx 64, 151
LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx 64, 148
LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx xxxx 64, 145
LATA LATA7
(8)
LATA6
(8)
LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 xxxx xxxx 64, 142
PORTJ
(7)
RJ7 RJ6 RJ5 RJ4 RJ3 RJ2 RJ1 RJ0 xxxx xxxx 65, 165
PORTH
(7)
RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0 0000 xxxx 65, 163
PORTG RDPU REPU RJPU
(7)
RG4 RG3 RG2 RG1 RG0 000x xxxx 65, 160
PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1
— x000 000- 65, 157
PORTE RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 xxxx xxxx 65, 154
PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx 65, 151
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 65, 148
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 65, 145
PORTA RA7
(8)
RA6
(8)
RA5 RA4 RA3 RA2 RA1 RA0 000x 0000 65, 142
SPBRGH1 EUSART1 Baud Rate Generator Register High Byte 0000 0000 65, 289
BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16
— WUE ABDEN 0100 0-00 65, 289
SPBRGH2 EUSART2 Baud Rate Generator Register High Byte 0000 0000 65, 289
BAUDCON2 ABDOVF RCIDL RXDTP TXCKP BRG16
— WUE ABDEN 0100 0-00 65, 289
TMR3H Timer3 Register High Byte xxxx xxxx 65, 210
TMR3L Timer3 Register Low Byte xxxx xxxx 65, 210
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC
TMR3CS TMR3ON 0000 0000 65, 210
TMR4 Timer4 Register 0000 0000 65, 209
PR4
(2)
/ Timer4 Period Register 1111 1111 65, 210
CVRCON
(3)
CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 65, 328
T4CON
— T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 -000 0000 65, 209
TABLE 6-5: REGISTER FILE SUMMARY (PIC18F87J11 FAMILY) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on
Page:
Legend: x = unknown; u = unchanged; — = unimplemented; q = value depends on condition; Bold = shared access SFRs
Note 1: Bit 21 of the PC is only available in Serial Programming modes.
2: Default (legacy) SFR at this address; available when WDTCON<4> = 0.
3: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1.
4: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
5: The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001.
6: Alternate names and definitions for these bits when the MSSP modules are operating in I
2
C™ Slave mode. See Section 20.4.3.2
“Address Masking Modes” for details.
7: These bits and/or registers are only available in 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 80-pin devices.
8:
These bits are only available in select oscillator modes (FOSC2 Configuration bit = 0 ); otherwise, they are unimplemented.
9: The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different
functions determined by the module’s operating mode. See Section 12.1.2 “Data Registers” for more information.