Datasheet

 2007-2012 Microchip Technology Inc. DS39778E-page 83
PIC18F87J11 FAMILY
FSR2H — — — — Indirect Data Memory Address Pointer 2 High Byte ---- 0000 62, 89
FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 62, 89
STATUS
— — —NOVZDCC---x xxxx 62, 87
TMR0H Timer0 Register High Byte 0000 0000 62, 195
TMR0L Timer0 Register Low Byte xxxx xxxx 62, 195
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 62, 194
OSCCON
(2)
/ IDLEN IRCF2 IRCF1 IRCF0 OSTS
(4)
— SCS1 SCS0 0110 q100 62, 38
REFOCON
(3)
ROON — ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 0-00 0000 62, 45
CM1CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 0001 1111 62, 320
CM2CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 0001 1111 62, 320
RCON IPEN
—CMRI TO PD POR BOR 0-11 1100 60, 62,
133
TMR1H
(2)
/ Timer1 Register High Byte xxxx xxxx 62, 198
ODCON1
(3)
— — — CCP5OD CCP4OD ECCP3OD ECCP2OD ECCP1OD ---0 0000 62, 138
TMR1L
(2)
/ Timer1 Register Low Byte xxxx xxxx 62, 198
ODCON2
(3)
— — — — — —U2ODU1OD---- --00 62, 138
T1CON
(2)
/ RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 62, 198
ODCON3
(3)
— — — — — — SPI2OD SPI1OD ---- --00 62, 138
TMR2
(2)
/ Timer2 Register 0000 0000 62, 203
PADCFG1
(3)
— — — — — — —PMPTTL---- ---0 62, 139
PR2
(2)
/ Timer2 Period Register 1111 1111 62, 203
MEMCON
(3,7)
EDBIS —WAIT1WAIT0— —WM1WM00-00 --00 62, 106
T2CON
— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 62, 203
SSP1BUF MSSP1 Receive Buffer/Transmit Register xxxx xxxx 62, 238,
248
SSP1ADD/ MSSP1 Address Register (I
2
C™ Slave mode), MSSP1 Baud Rate Reload Register (I
2
C Master mode) 0000 0000 62, 248
SSP1MSK
(5)
MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 0000 0000 62, 255
SSP1STAT SMP CKE D/A
PSR/WUA BF 0000 0000 62, 239,
249
SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 62, 240,
250
SSP1CON2
GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN/ SEN 0000 0000 62, 251,
283
GCEN
ACKSTAT ADMSK5
(6)
ADMSK4
(6)
ADMSK3
(6)
ADMSK2
(6)
ADMSK1
(6)
SEN
ADRESH A/D Result Register High Byte xxxx xxxx 63, 309
ADRESL A/D Result Register Low Byte xxxx xxxx 63, 309
ADCON0
(2)
/ VCFG1 VCFG0 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 63, 309
ANCON1
(3)
PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 0000 0000 63, 311
ADCON1
(2)
/ ADFM ADCAL ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0000 0000 63, 310
ANCON0
(3)
PCFG7 PCFG6 — PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 00-0 0000 63, 311
WDTCON REGSLP LVDSTAT
—ADSHR— — —SWDTEN0x-0 ---0 63, 339
TABLE 6-5: REGISTER FILE SUMMARY (PIC18F87J11 FAMILY) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on
Page:
Legend: x = unknown; u = unchanged; — = unimplemented; q = value depends on condition; Bold = shared access SFRs
Note 1: Bit 21 of the PC is only available in Serial Programming modes.
2: Default (legacy) SFR at this address; available when WDTCON<4> = 0.
3: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1.
4: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
5: The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001.
6: Alternate names and definitions for these bits when the MSSP modules are operating in I
2
C™ Slave mode. See Section 20.4.3.2
“Address Masking Modes” for details.
7: These bits and/or registers are only available in 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 80-pin devices.
8:
These bits are only available in select oscillator modes (FOSC2 Configuration bit = 0 ); otherwise, they are unimplemented.
9: The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different
functions determined by the module’s operating mode. See Section 12.1.2 “Data Registers” for more information.