Datasheet

PIC18F87J11 FAMILY
DS39778E-page 82  2007-2012 Microchip Technology Inc.
TABLE 6-5: REGISTER FILE SUMMARY (PIC18F87J11 FAMILY)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on
Page:
TOSU
— — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 61, 71
TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 61, 71
TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 61, 71
STKPTR STKFUL STKUNF
— SP4 SP3 SP2 SP1 SP0 00-0 0000 61, 72
PCLATU
— —bit 21
(1)
Holding Register for PC<20:16> ---0 0000 61, 71
PCLATH Holding Register for PC<15:8> 0000 0000 61, 71
PCL PC Low Byte (PC<7:0>) 0000 0000 61, 71
TBLPTRU
— — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 61, 104
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 61, 104
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 61, 104
TABLAT Program Memory Table Latch 0000 0000 61, 104
PRODH Product Register High Byte xxxx xxxx 61, 117
PRODL Product Register Low Byte xxxx xxxx 61, 117
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 61, 121
INTCON2 RBPU
INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 1111 1111 61, 121
INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF 1100 0000 61, 121
INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 61, 89
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 61, 90
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) N/A 61, 90
PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 61, 90
PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –
value of FSR0 offset by W
N/A 61, 90
FSR0H
— — — — Indirect Data Memory Address Pointer 0 High Byte ---- 0000 61, 89
FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 61, 89
WREG Working Register xxxx xxxx 61, 73
INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 61, 89
POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 61, 90
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) N/A 61, 90
PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 61, 90
PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –
value of FSR1 offset by W
N/A 61, 90
FSR1H
— — — — Indirect Data Memory Address Pointer 1 High Byte ---- 0000 61, 89
FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx 61, 89
BSR
— — — — Bank Select Register ---- 0000 61, 76
INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 62, 89
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 62, 90
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A 62, 90
PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 62, 90
PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –
value of FSR2 offset by W
N/A 62, 90
Legend: x = unknown; u = unchanged; — = unimplemented; q = value depends on condition; Bold = shared access SFRs
Note 1: Bit 21 of the PC is only available in Serial Programming modes.
2: Default (legacy) SFR at this address; available when WDTCON<4> = 0.
3: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1.
4: Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
5: The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001.
6: Alternate names and definitions for these bits when the MSSP modules are operating in I
2
C™ Slave mode. See Section 20.4.3.2
“Address Masking Modes” for details.
7: These bits and/or registers are only available in 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 80-pin devices.
8:
These bits are only available in select oscillator modes (FOSC2 Configuration bit = 0 ); otherwise, they are unimplemented.
9: The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different
functions determined by the module’s operating mode. See Section 12.1.2 “Data Registers” for more information.