Datasheet

PIC18F87J11 FAMILY
DS39778E-page 454  2007-2012 Microchip Technology Inc.
F
Fail-Safe Clock Monitor ............................................331, 343
Exiting ......................................................................344
Interrupts in Power-Managed Modes ....................... 344
POR or Wake-up From Sleep .................................. 344
WDT During Oscillator Failure ................................. 343
Fast Register Stack ............................................................73
Firmware Instructions .......................................................347
Flash Configuration Words ...............................................331
Flash Program Memory ......................................................95
Associated Registers ...............................................104
Control Registers .......................................................96
EECON1 and EECON2 ..................................... 96
TABLAT (Table Latch) Register .........................98
TBLPTR (Table Pointer) Register ...................... 98
Erase Sequence ...................................................... 100
Erasing .....................................................................100
Operation During Code-Protect ...............................104
Reading ......................................................................99
Table Pointer
Boundaries Based on Operation ........................98
Table Pointer Boundaries .......................................... 98
Table Reads and Table Writes .................................. 95
Write Sequence .......................................................101
Write Sequence (Word Programming) .....................103
Writing ......................................................................101
Unexpected Termination .................................. 104
Write Verify ...................................................... 104
FSCM. See Fail-Safe Clock Monitor.
G
GOTO ...............................................................................368
H
Hardware Multiplier ..........................................................117
8 x 8 Multiplication Algorithms .................................117
Operation .................................................................117
Performance Comparison (table) .............................117
I
I/O Ports ...........................................................................135
Input Pull-up Configuration ...................................... 136
Open-Drain Outputs ................................................. 137
Pin Capabilities ........................................................135
I
2
C Mode (MSSP)
Acknowledge Sequence Timing ...............................277
Associated Registers ...............................................283
Baud Rate Generator ...............................................270
Bus Collision
During a Repeated Start Condition .................. 281
During a Stop Condition ................................... 282
Clock Arbitration .......................................................271
Clock Stretching ....................................................... 263
10-Bit Slave Receive Mode (SEN = 1) ............. 263
10-Bit Slave Transmit Mode ............................. 263
7-Bit Slave Receive Mode (SEN = 1) ............... 263
7-Bit Slave Transmit Mode ............................... 263
Clock Synchronization and the CKP bit ...................264
Effects of a Reset .....................................................278
General Call Address Support ................................. 267
I
2
C Clock Rate w/BRG .............................................270
Master Mode ............................................................ 268
Operation ......................................................... 269
Reception ........................................................ 274
Repeated Start Condition Timing .................... 273
Start Condition Timing ..................................... 272
Transmission ................................................... 274
Multi-Master Communication, Bus Collision
and Arbitration ................................................. 278
Multi-Master Mode ................................................... 278
Operation ................................................................. 253
Read/Write
Bit Information (R/W Bit) ............... 253, 256
Registers ................................................................. 248
Serial Clock (RC3/SCKx/SCLx) ............................... 256
Slave Mode .............................................................. 253
Address Masking Modes
5-Bit ......................................................... 254
7-Bit ......................................................... 255
Addressing ....................................................... 253
Reception ........................................................ 256
Transmission ................................................... 256
Sleep Operation ....................................................... 278
Stop Condition Timing ............................................. 277
INCF ................................................................................ 368
INCFSZ ............................................................................ 369
In-Circuit Debugger .......................................................... 345
In-Circuit Serial Programming (ICSP) ...................... 331, 345
Indexed Literal Offset Addressing
and Standard PIC18 Instructions ............................. 394
Indexed Literal Offset Mode ............................................. 394
Indirect Addressing ............................................................ 89
INFSNZ ............................................................................ 369
Initialization Conditions for all Registers ...................... 61–66
Instruction Cycle ................................................................ 74
Clocking Scheme ....................................................... 74
Flow/Pipelining ........................................................... 74
Instruction Set .................................................................. 347
ADDLW .................................................................... 353
ADDWF .................................................................... 353
ADDWF (Indexed Literal Offset Mode) .................... 395
ADDWFC ................................................................. 354
ANDLW .................................................................... 354
ANDWF .................................................................... 355
BC ............................................................................ 355
BCF ......................................................................... 356
BN ............................................................................ 356
BNC ......................................................................... 357
BNN ......................................................................... 357
BNOV ...................................................................... 358
BNZ ......................................................................... 358
BOV ......................................................................... 361
BRA ......................................................................... 359
BSF .......................................................................... 359
BSF (Indexed Literal Offset Mode) .......................... 395
BTFSC ..................................................................... 360
BTFSS ..................................................................... 360
BTG ......................................................................... 361
BZ ............................................................................ 362
CALL ........................................................................ 362
CLRF ....................................................................... 363
CLRWDT ................................................................. 363
COMF ...................................................................... 364