Datasheet

PIC18F87J11 FAMILY
DS39778E-page 428  2007-2012 Microchip Technology Inc.
FIGURE 28-12: PARALLEL MASTER PORT WRITE TIMING DIAGRAM
TABLE 28-18: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS
Param.
No
Symbol Characteristics Min Typ Max Units
PM11 PMWR Pulse Width — 0.5 T
CY —ns
PM12 Data Out Valid before PMWR or PMENB
Goes Inactive (data setup time)
———ns
PM13 PMWR or PMEMB Invalid to Data Out
Invalid (data hold time)
———ns
PM16 PMCSx Pulse Width T
CY – 5 — — ns
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2
System
PMALL/
PMD<7:0>
Address
PMA<18:13>
Operating Conditions: 2.0V < VCC < 3.6V, -40°C < TA < +85°C unless otherwise stated.
PMWR
PMCS<2:1>
PMRD
Clock
PM12
PM13
PM11
PM16
Data
Address<7:0>
PMALH