Datasheet

PIC18F87J11 FAMILY
DS39778E-page 422 2007-2012 Microchip Technology Inc.
FIGURE 28-7: PROGRAM MEMORY READ TIMING DIAGRAM
TABLE 28-11: PROGRAM MEMORY READ TIMING REQUIREMENTS
Param.
No
Symbol Characteristics Min Typ Max Units
150 TadV2alL Address Out Valid to ALE 
(address setup time)
0.25 TCY – 10 ns
151 TalL2adl ALE to Address Out Invalid
(address hold time)
5—ns
155 TalL2oeL ALE to OE
10 0.125 TCY —ns
160 TadZ2oeL AD high-Z to OE
(bus release to OE)0ns
161 ToeH2adD OE
to AD Driven 0.125 TCY – 5 ns
162 TadV2oeH Least Significant Data Valid Before OE

(data setup time)
20 ns
163 ToeH2adl OE
to Data In Invalid (data hold time) 0 ns
164 TalH2alL ALE Pulse Width 0.25 T
CY —ns
165 ToeL2oeH OE
Pulse Width 0.5 TCY – 5 0.5 TCY —ns
166 TalH2alH ALE to ALE (cycle time) T
CY —ns
167 Tacc Address Valid to Data Valid 0.75 T
CY – 25 ns
168 Toe OE
to Data Valid 0.5 TCY – 25 ns
169 TalL2oeH ALE to OE
0.625 TCY – 10 0.625 TCY + 10 ns
171 TalH2csL Chip Enable Active to ALE 0.25 T
CY – 20 ns
171A TubL2oeH AD Valid to Chip Enable Active 10 ns
Address
Q1 Q2 Q3 Q4 Q1 Q2
OSC1
ALE
OE
166
160
165
161
151
162
163
AD<15:0>
167
168
155
Address
Address
150
A<19:16>
Address
169
BA0
CE
171
171A
Operating Conditions: 2.0V < VCC < 3.6V, -40°C < TA < +125°C unless otherwise stated.
164
Data from External