Datasheet

PIC18F87J11 FAMILY
DS39778E-page 318  2007-2012 Microchip Technology Inc.
TABLE 22-2: SUMMARY OF A/D REGISTERS
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page:
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 61
PIR1
PMPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 64
PIE1 PMPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 64
IPR1 PMPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 64
PIR2
OSCFIF CM2IF CM1IF — BCL1IF LVDIF TMR3IF CCP2IF 64
PIE2 OSCFIE CM2IE CM1IE — BCL1IE LVDIE TMR3IE CCP2IE 64
IPR2 OSCFIP CM2IP CM1IP — BCL1IP LVDIP TMR3IP CCP2IP 64
ADRESH A/D Result Register High Byte 63
ADRESL A/D Result Register Low Byte 63
ADCON0
(2)
VCFG1 VCFG0 CHS3 CHS3 CHS1 CHS0 GO/DONE ADON 63
ANCON0
(3)
PCFG7 PCFG6 — PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 63
ADCON1
(2)
ADFM ADCAL ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 63
ANCON1
(3)
PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 63
CCP2CON P2M1 P2M0 DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 63
PORTA
RA7
(4)
RA6
(4)
RA5 RA4 RA3 RA2 RA1 RA0 65
TRISA TRISA7
(4)
TRISA6
(4)
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 64
PORTF RF7RF6RF5RF4RF3RF2RF1 — 65
TRISF
TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 — 64
PORTH
(1)
RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0 65
TRISH
(1)
TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 64
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: This register is not implemented on 64-pin devices.
2: Default (legacy) SFR at this address, available when WDTCON<4> = 0.
3: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1.
4: These bits are only available in select oscillator modes (FOSC2 Configuration bit = 0); otherwise, they are
unimplemented.