Datasheet
PIC18F87J11 FAMILY
DS39778E-page 168 2007-2012 Microchip Technology Inc.
12.1 Module Registers
The PMP module has a total of 14 Special Function
Registers for its operation, plus one additional register
to set configuration options. Of these, 8 registers are
used for control and 6 are used for PMP data transfer.
12.1.1 CONTROL REGISTERS
The eight PMP Control registers are:
• PMCONH and PMCONL
• PMMODEH and PMMODEL
• PMSTATL and PMSTATH
• PMEH and PMEL
The PMCON registers (Register 12-1 and
Register 12-2) control basic module operations, includ-
ing turning the module on or off. They also configure
address multiplexing and control strobe configuration.
The PMMODE registers (Register 12-3 and
Register 12-4) configure the various Master and Slave
Operating modes, the data width and interrupt
generation.
The PMEH and PMEL registers (Register 12-5 and
Register 12-6) configure the module’s operation at the
hardware (I/O pin) level.
The PMSTAT registers (Register 12-7 and
Register 12-8) provide status flags for the module’s
input and output buffers, depending on the operating
mode.
REGISTER 12-1: PMCONH: PARALLEL PORT CONTROL HIGH BYTE REGISTER
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PMPEN — PSIDL
ADRMUX1 ADRMUX0
PTBEEN PTWREN PTRDEN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 PMPEN: Parallel Master Port Enable bit
1 = PMP is enabled
0 = PMP is disabled, no off-chip access is performed
bit 6 Unimplemented: Read as ‘0’
bit 5 PSIDL: Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 4-3 ADRMUX<1:0>: Address/Data Multiplexing Selection bits
11 = Reserved
10 = All 16 bits of address are multiplexed on PMD<7:0> pins
01 = Lower 8 bits of address are multiplexed on PMD<7:0> pins, upper 8 bits are on PMA<15:8>
00 = Address and data appear on separate pins
bit 2 PTBEEN: Byte Enable Port Enable bit (16-bit Master mode)
1 = PMBE port is enabled
0 = PMBE port is disabled
bit 1 PTWREN: Write Enable Strobe Port Enable bit
1 = PMWR/PMENB port is enabled
0 = PMWR/PMENB port is disabled
bit 0 PTRDEN: Read/Write Strobe Port Enable bit
1 = PMRD/PMWR port is enabled
0 = PMRD/PMWR port is disabled