Datasheet

 2007-2012 Microchip Technology Inc. DS39778E-page 141
PIC18F87J11 FAMILY
TABLE 11-4: PORTA FUNCTIONS
Pin Name Function
TRIS
Setting
I/O
I/O
Type
Description
RA0/AN0 RA0 0 O DIG LATA<0> data output; not affected by analog input.
1 I TTL PORTA<0> data input; disabled when analog input is enabled.
AN0 1 I ANA A/D Input Channel 0. Default input configuration on POR; does not
affect digital output.
RA1/AN1 RA1 0 O DIG LATA<1> data output; not affected by analog input.
1 I TTL PORTA<1> data input; disabled when analog input is enabled.
AN1 1 I ANA A/D Input Channel 1. Default input configuration on POR; does not
affect digital output.
RA2/AN2/V
REF-RA2 0 O DIG LATA<2> data output; not affected by analog input. Disabled when
CV
REF output is enabled.
1 I TTL PORTA<2> data input. Disabled when analog functions enabled;
disabled when CV
REF output is enabled.
AN2 1 I ANA A/D Input Channel 2. Default input configuration on POR; not affected
by analog output.
V
REF- 1 I ANA A/D low reference voltage input.
RA3/AN3/V
REF+RA3 0 O DIG LATA<3> data output; not affected by analog input.
1 I TTL PORTA<3> data input; disabled when analog input is enabled.
AN3 1 I ANA A/D Input Channel 3. Default input configuration on POR.
V
REF+ 1 I ANA A/D high reference voltage input.
RA4/PMD5/
T0CKI/
RA4 0 O DIG LATA<4> data output.
1 I ST PORTA<4> data input; default configuration on POR.
PMD5
(1)
x O DIG Parallel Master Port data output.
x I TTL Parallel Master Port data output.
T0CKI x I ST Timer0 clock input.
RA5/PMD4/AN4 RA5 0 O DIG LATA<5> data output; not affected by analog input.
1 I TTL PORTA<5> data input; disabled when analog input is enabled.
PMD4
(1)
x O DIG Parallel Master Port data output.
x I TTL Parallel Master Port data output.
AN4 1 I ANA A/D Input Channel 4. Default configuration on POR.
OSC2/CLKO/
RA6
OSC2 x O ANA Main oscillator feedback output connection (HS and HSPLL modes).
CLKO x O DIG System cycle clock output, F
OSC/4 (EC, ECPLL, INTIO1 and INTPLL1
modes).
RA6 0 O DIG LATA<6> data output; disabled when FOSC2 Configuration bit is set.
1 I TTL PORTA<6> data input; disabled when FOSC2 Configuration bit is set.
OSC1/CLKI/
RA7
OSC1 x I ANA Main oscillator input connection (HS and HSPLL modes).
CLKI x I ANA Main external clock source input (EC and ECPLL modes).
RA7 0 O DIG LATA<7> data output; disabled when FOSC2 Configuration bit is set.
1 I TTL PORTA<7> data input; disabled when FOSC2 Configuration bit is set.
Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: Alternate PMP configuration when the PMPMX Configuration bit is ‘0’; available on 80-pin devices only.