Datasheet

 2003-2013 Microchip Technology Inc. DS30491D-page 67
PIC18F6585/8585/6680/8680
TABLE 4-3: REGISTER FILE SUMMARY
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on page:
TOSU — — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 36, 54
TOSH Top-of-Stack High Byte (TOS<15:8>)
0000 0000 36, 54
TOSL Top-of-Stack Low Byte (TOS<7:0>)
0000 0000 36, 54
STKPTR STKFUL STKUNF
— Return Stack Pointer 00-0 0000 36, 55
PCLATU
— — bit 21 Holding Register for PC<20:16> --00 0000 36, 56
PCLATH Holding Register for PC<15:8>
0000 0000 36, 56
PCL PC Low Byte (PC<7:0>)
0000 0000 36, 56
TBLPTRU
— —bit 21
(2)
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 36, 86
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
0000 0000 36, 86
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
0000 0000 36, 86
TABLAT Program Memory Table Latch
0000 0000 36, 86
PRODH Product Register High Byte
xxxx xxxx 36, 107
PRODL Product Register Low Byte
xxxx xxxx 36, 107
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
0000 000x 36, 111
INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP
1111 1111 36, 112
INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF
1100 0000 36, 113
INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) n/a 79
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) n/a 79
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) n/a 79
PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) n/a 79
PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented
(not a physical register) – value of FSR0 offset by value in WREG
n/a 79
FSR0H
— — — — Indirect Data Memory Address Pointer 0 High Byte ---- 0000 36, 79
FSR0L Indirect Data Memory Address Pointer 0 Low Byte
xxxx xxxx 36, 79
WREG Working Register
xxxx xxxx 36
INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) n/a 79
POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) n/a 79
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) n/a 79
PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) n/a 79
PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented
(not a physical register) – value of FSR1 offset by value in WREG
n/a 79
FSR1H
— — — — Indirect Data Memory Address Pointer 1 High Byte ---- 0000 37, 79
FSR1L Indirect Data Memory Address Pointer 1 Low Byte
xxxx xxxx 37, 79
BSR
— — — — Bank Select Register ---- 0000 37, 78
INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) n/a 79
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) n/a 79
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) n/a 79
PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) n/a 79
PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented
(not a physical register) – value of FSR2 offset by value in WREG
n/a 79
FSR2H
— — — — Indirect Data Memory Address Pointer 2 High Byte ---- 0000 37, 79
FSR2L Indirect Data Memory Address Pointer 2 Low Byte
xxxx xxxx 37, 79
Legend: x = unknown, u = unchanged, – = unimplemented, q = value depends on condition
Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator
modes.
2: Bit 21 of the TBLPTRU allows access to the device configuration bits.
3: These registers are unused on PIC18F6X80 devices; always maintain these clear.
4: These bits have multiple functions depending on the CAN module mode selection.
5: Meaning of this register depends on whether this buffer is configured as transmit or receive.
6: RG5 is available as an input when MCLR
is disabled.
7: This register reads all ‘0’s until the ECAN module is set up in Mode 1 or Mode 2.
18F8680.book Page 67 Tuesday, January 29, 2013 1:32 PM