Datasheet

PIC18F6585/8585/6680/8680
DS30491D-page 50  2003-2013 Microchip Technology Inc.
FIGURE 3-6: SLOW RISE TIME (MCLR TIED TO VDD VIA 1 kRESISTOR)
FIGURE 3-7: TIME-OUT SEQUENCE ON POR W/ PLL ENABLED
(MCLR TIED TO VDD VIA 1 kRESISTOR)
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
0V
1V
5V
T
PWRT
TOST
TPWRT
TOST
VDD
MCLR
IINTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
PLL TIME-OUT
TPLL
Note: TOST = 1024 clock cycles.
T
PLL  2 ms max. First three stages of the PWRT timer.
18F8680.book Page 50 Tuesday, January 29, 2013 1:32 PM