Datasheet

PIC18F6585/8585/6680/8680
DS30491D-page 484  2003-2013 Microchip Technology Inc.
Timer2 ............................................................................... 162
Associated Registers ................................................163
Operation .................................................................. 162
Postscaler. See Postscaler, Timer2.
PR2 Register............................................. 162, 173, 177
Prescaler. See Prescaler, Timer2.
SSP Clock Shift................................................. 162, 163
TMR2 Register..........................................................162
TMR2 to PR2 Match
Interrupt..................................... 162, 163, 173, 177
Timer3 ............................................................................... 164
Associated Registers ................................................166
Operation .................................................................. 165
Oscillator ...........................................................164, 166
Overflow Interrupt .............................................164, 166
Special Event Trigger
(CCP) ................................................................166
TMR3H Register .......................................................164
TMR3L Register........................................................ 164
Timing Diagrams
A/D Conversion......................................................... 447
Acknowledge Sequence ........................................... 222
Asynchronous Reception ..........................................241
Asynchronous Transmission..................................... 238
Asynchronous Transmission
(Back to Back)................................................... 238
Automatic Baud Rate
Calculation ........................................................236
Auto-Wake-up Bit (WUE) During
Normal Operation..............................................242
Auto-Wake-up Bit (WUE)
During Sleep .....................................................242
Baud Rate Generator with
Clock Arbitration................................................ 216
BRG Reset Due to SDA Arbitration During
Start Condition .................................................. 225
Brown-out Reset (BOR) ............................................ 433
Bus Collision During a Repeated
Start Condition (Case 1) ................................... 226
Bus Collision During a Repeated
Start Condition (Case 2) ................................... 226
Bus Collision During a Stop Condition
(Case 1) ............................................................ 227
Bus Collision During a Stop Condition
(Case 2) ............................................................ 227
Bus Collision During Start Condition
(SCL = 0) .......................................................... 225
Bus Collision During Start Condition
(SDA only)......................................................... 224
Bus Collision for Transmit and
Acknowledge.................................................... 223
Capture/Compare/PWM
(All CCP Modules) ............................................435
CLKO and I/O ........................................................... 429
Clock Synchronization .............................................. 209
Clock/Instruction Cycle ............................................... 56
Example SPI Master Mode
(CKE = 0) .......................................................... 437
Example SPI Master Mode
(CKE = 1) .......................................................... 438
Example SPI Slave Mode
(CKE = 0).......................................................... 439
Example SPI Slave Mode
(CKE = 1).......................................................... 440
External Clock (All Modes
except PLL) ...................................................... 428
External Program Memory Bus
(16-bit Mode) ...................................................... 99
First Start Bit............................................................. 217
Full-Bridge PWM Output........................................... 181
Half-Bridge PWM Output .......................................... 180
I
2
C Bus Data............................................................. 441
I
2
C Bus Start/Stop Bits ............................................. 441
I
2
C Master Mode (7 or
10-bit Transmission)......................................... 220
I
2
C Master Mode
(7-bit Reception)............................................... 221
I
2
C Slave Mode (10-bit Reception,
SEN = 0)........................................................... 206
I
2
C Slave Mode (10-bit Reception,
SEN = 1)........................................................... 211
I
2
C Slave Mode
(10-bit Transmission)........................................ 207
I
2
C Slave Mode (7-bit Reception,
SEN = 0)........................................................... 204
I
2
C Slave Mode (7-bit Reception,
SEN = 1)........................................................... 210
I
2
C Slave Mode
(7-bit Transmission).......................................... 205
Low-Voltage Detect .................................................. 272
Master SSP I
2
C Bus Data......................................... 443
Master SSP I
2
C Bus
Start/Stop Bits................................................... 443
Parallel Slave Port
(PIC18FXX8X).................................................. 436
Parallel Slave Port (PSP)
Read ................................................................. 154
Parallel Slave Port (PSP)
Write ................................................................. 153
Program Memory Read ............................................ 430
Program Memory Write............................................. 431
PWM Auto-Shutdown (PRSEN = 0,
Auto-Restart Disabled) ..................................... 186
PWM Auto-Shutdown (PRSEN = 1,
Auto-Restart Enabled)...................................... 186
PWM Output ............................................................. 173
Repeat Start Condition ............................................. 218
Reset, Watchdog Timer (WDT),
Oscillator Start-up Timer (OST)
and Power-up Timer (PWRT) ........................... 432
Send Break Character Sequence............................. 243
Slave Mode General Call Address
Sequence (7 or 10-bit
Address Mode) ................................................. 212
Slave Synchronization.............................................. 195
Slow Rise Time (MCLR
Tied to VDD
via 1 kResistor) ............................................... 50
SPI Mode (Master Mode).......................................... 194
SPI Mode (Slave Mode with
CKE = 0)........................................................... 196
18F8680.book Page 484 Tuesday, January 29, 2013 1:32 PM