Datasheet

 2003-2013 Microchip Technology Inc. DS30491D-page 445
PIC18F6585/8585/6680/8680
FIGURE 27-23: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 27-23: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 27-24: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 27-24: USART SYNCHRONOUS RECEIVE REQUIREMENTS
121
121
120
122
RC6/TX/CK
RC7/RX/DT
pin
pin
Note: Refer to Figure 27-5 for load conditions.
Param.
No.
Symbol Characteristic Min Max Units Conditions
120 T
CKH2DTV SYNC XMIT (MASTER & SLAVE)
Clock High to Data Out Valid PIC18FXX8X — 40 ns
PIC18LFXX8X — 100 ns
121 T
CKRF Clock Out Rise Time and Fall Time
(Master mode)
PIC18FXX8X — 20 ns
PIC18LFXX8X — 50 ns
122 T
DTRF Data Out Rise Time and Fall Time PIC18FXX8X — 20 ns
PIC18LFXX8X — 50 ns
125
126
RC6/TX/CK
RC7/RX/DT
pin
pin
Note: Refer to Figure 27-5 for load conditions.
Param.
No.
Symbol Characteristic Min Max Units Conditions
125 T
DTV2CKL SYNC RCV (MASTER & SLAVE)
Data Hold before CK  (DT hold time) 10 — ns
126 T
CKL2DTL Data Hold after CK  (DT hold time) 15 — ns
18F8680.book Page 445 Tuesday, January 29, 2013 1:32 PM