Datasheet

 2003-2013 Microchip Technology Inc. DS30491D-page 433
PIC18F6585/8585/6680/8680
FIGURE 27-11: BROWN-OUT RESET TIMING
TABLE 27-11: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
FIGURE 27-12: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
VDD
BVDD
35
VBGAP = 1.2V
V
IRVST
Enable Internal
Internal Reference
36
Reference Voltage
Voltage Stable
Param.
No.
Symbol Characteristic Min Typ Max Units Conditions
30 T
MCLMCLR Pulse Width (low) 2 — — s
31 T
WDT Watchdog Timer Time-out Period
(No Postscaler)
71833ms
32 T
OST Oscillation Start-up Timer Period 1024 TOSC — 1024 TOSC —TOSC = OSC1 period
33 T
PWRT Power up Timer Period 28 72 132 ms
34 T
IOZ I/O High-Impedance from MCLR Low
or Watchdog Timer Reset
—2—s
35 T
BOR Brown-out Reset Pulse Width 200 — — sVDD  BVDD (see )
36 T
IVRST Time for Internal Reference
Voltage to become stable
—2050 s
37 T
LVD Low-Voltage Detect Pulse Width 200 — — sVDD  VLVD
Note: Refer to Figure 27-5 for load conditions.
46
47
45
48
41
42
40
T0CKI
T1OSO/T1CKI
TMR0 or
TMR1
18F8680.book Page 433 Tuesday, January 29, 2013 1:32 PM