Datasheet

PIC18F6585/8585/6680/8680
DS30491D-page 432  2003-2013 Microchip Technology Inc.
TABLE 27-10: PROGRAM MEMORY WRITE TIMING REQUIREMENTS (VDD = 4.2 TO 5.5V)
FIGURE 27-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
Param.
No.
Symbol Characteristics Min Typ Max Units
150 T
ADV2ALL Address Out Valid to ALE (address setup time) 0.25 TCY – 10 — — ns
151 T
ALL2ADL ALE  to Address Out Invalid (address hold time) 5 — — ns
153 T
WRH2ADL WRn  to Data Out Invalid (data hold time) 5 — — ns
154 T
WRL WRn Pulse Width 0.5 TCY – 5 0.5 TCY —ns
156 T
ADV2WRH Data Valid before WRn (data setup time) 0.5 TCY – 10 — — ns
157 T
BSV2WRL Byte Select Valid before WRn (byte select setup time) 0.25 TCY ——ns
157A T
WRH2BSIWRn  to Byte Select Invalid (byte select hold time) 0.125 TCY – 5 — — ns
166 T
ALH2ALHALE  to ALE  (cycle time) — 0.25 TCY —ns
171 T
ALH2CSL Chip Enable Active to ALE  ——10ns
171A T
UBL2OEH AD Valid to Chip Enable Active 0.25 TCY – 20 — — ns
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
33
32
30
31
34
I/O pins
34
Note: Refer to Figure 27-5 for load conditions.
18F8680.book Page 432 Tuesday, January 29, 2013 1:32 PM